IC-HT datasheet(17/42 Pages) ICHAUS

17 / 42 page

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iC-HT

DUAL CW LASER DIODE DRIVER

Rev A1, Page 17/42

10 Bit

8 Bit

10 Bit

ACC

APC

RACC1

..10 nF..

255

PLR1

CI1

..750mA

8 Bit

LASER CHANNEL 1

MRL1

MDA1

AGND1

CIL1

CI1

LDK1

DCO

ECIE1

VDD

LDK1

ADSNF1

OVC1

DISP1

EMC

CI1

..750mA

Figure 6: ACC with monitor photodiode

The Regulator

In MCU mode the control can be carried out without

the need of external capacitor. This allows a fast re-

sponse of the regulator. The speed of the regulator’s

response and stability can be conﬁgured using three

bits (COMPx), providing a current compensation fac-

tor.

COMP1

Addr. 0x13; bit 6:4

R/W 011

000

Minimum compensation current for the channel 1

regulator, slower response

. . .

111

Maximum compensation current for the channel 1

regulator, faster response

Table 30: Current compensation channel 1

COMP2

Addr. 0x18; bit 6:4

R/W 011

000

Minimum compensation current for the channel 2

regulator, slower response

. . .

111

Maximum compensation current for the channel 2

regulator, faster response

Table 31: Current compensation channel 2

Alternatively it is possible to use external capacitors

connected to pins CIx and CILx. In this case, register

bit ECIEx should be set to 1 and COMPx to its highest

value, "111".

ECIE1

Addr. 0x10; bit 1

R/W 0

External CI capacitor for channel 1 disconnected

External CI capacitor for channel 1 connected

Table 32: Enable external capacitor channel 1

ECIE2

Addr. 0x15; bit 1

R/W 0

External CI capacitor for channel 2 disconnected

External CI capacitor for channel 2 connected

Table 33: Enable external capacitor channel 2

The regulator is offset compensated in order to pre-

vent optical power drifts. Offset compensation can be

disabled by setting register bit EOCx to 0.

EOC1

Addr. 0x10; bit 4

R/W 1

Channel 1 regulator offset compensation disabled

Channel 1 regulator offset compensation enabled

Table 34: Enable offset compensation channel 1

EOC2

Addr. 0x15; bit 4

R/W 1

Channel 2 regulator offset compensation disabled

Channel 2 regulator offset compensation enabled

Table 35: Enable offset compensation channel 2

An internal oscillator is used for the offset compensa-

tion. A watchdog timer (WDT) is included in order to

monitor proper function of the oscillator. If an error

is detected by the WDT, the laser channels are dis-

abled, OSCERR error bit is set in STATUS0 register

and the error event is signaled at pin NCHK. This error

signaling can be suppressed using the mask register

bit MOSCERR (set to 1).

MOSCERR

Addr. 0x1D; bit 0

R/W 0

Oscillator error (watchdog) will be signaled at

NCHK

Oscillator error (watchdog) will not be signaled at

NCHK

Table 36: Oscillator error mask

iC-HT monitors the saturation voltage of the regula-

tor´s output transistor at pin LDKx. The LDK satura-

tion threshold can be conﬁgured through register bits

RLDKSx.

RLDKS1

Addr. 0x13; bit 3:2

R/W 00

V(LDK1) < 0.5 V sets the LDKSAT1 alarm bit

V(LDK1) < 0.8 V sets the LDKSAT1 alarm bit

V(LDK1) < 1.0 V sets the LDKSAT1 alarm bit

V(LDK1) < 1.2 V sets the LDKSAT1 alarm bit

Table 37: LDK saturation threshold selection channel

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