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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IC-HT датащи(PDF) 21 Page - IC-Haus GmbH |
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IC-HT датащи(HTML) 21 Page - IC-Haus GmbH |
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21 / 42 page  prel imin ary prel imin ary iC-HT DUAL CW LASER DIODE DRIVER Rev A1, Page 21/42 255 R 8 Bit ..10 nF.. TEMPERATURE MONITOR 8 Bit VDD REGULATOR LASER CHANNEL 1 LASER CHANNEL 2 DUAL CW LASER DIODE DRIVER RM1 ADC2(7:0) ADCC1(2:0) 0x10 0x1F 0x30 0x3F 1μF IO DRIVERS REGISTERS SPI/I2C SLAVE RAM 10 Bit A D 8 Bit A D 0x02 TEMP(7:0) 0x11 ILIM1(7:0) 0x13 REF1(9:8) 0x14 REF1(7:0) 0x12 RMD1(7:0) 0x16 ILIM2(7:0) 0x18 0 TIMER OSCILLATOR LASER CONTROL ACC APC PLR1 REF2(9:8) 0x19 REF2(7:0) 0x17 RMD2(7:0) INTEGRITY RAM CHECK VB UNDERVOLTAGE VDD UNDERVOLTAGE OVC PODO OVT MEMERR 10 Bit A D 0x10 0x03 ADC1(9:8) 0x04 ADC1(7:0) 0x05 ADC2(9:8) 0x06 1μF CFGTIMO WATCHDOG WATCHDOG + - CVDD CVB + - N ..750mA CI1 MISO/SDA INS/WKR NSTBY EC1 VB VDD LDK1 GND T.PAD EACC1 ADSNF1 OVC1 DISP1 EMC CI AGND1 CI LDK1 2.8...8V VB CIL1 VDD GND REF MRL1 NCHK Check VB MRL2 MDA2 AGND2 CIL2 CI2 LDK2 MDA1 CI1 ECIE1 DCO EC2 EMC NCS/A1 MOSI/A0 SCLK/SCL N ..750mA CI1 CVDD CVB Figure 9: Additional photodiode in combined configuration SERIAL COMMUNICATION INTERFACES SPI slave interface The SPI slave interface is enabled by setting pin INS/WKR to lo and uses pins NCS/A1, SCLK/SCL, MISO/SDA and MOSI/A0. Pin NCS/A1 is the chip se- lect pin and must be set lo by the SPI master in order to start communication. Pins MISO/SDA and MOSI/A0 are the data communication lines and pin SCLK/SCL is the clock line generated by the SPI master (e.g. mi- crocontroller). The SPI protocol frames are shown in figure 10. A communication frame consists of one address byte and at least one data byte. Bits 7:6 of the address byte is the opcode used for selecting a read operation (set to "10") or a write (set to "01") operation. The remain- ing 6 bits are used for register addressing. It is possible to transmit several bytes consecutively, if the NCS signal is not reset and SCLK/SCL keeps clocking, as it is shown in figure 10. The address is in- ternally incremented after each transmitted byte. Once the address reaches the last register (0x3F), it is reset back to 0x00. 13 14 15 MOSI SPI READ COMMAND FRAME. OPCODE = 10, POLARITY = 0, PHASE = 0 SPI WRITE COMMAND FRAME. OPCODE = 01, POLARITY = 0, PHASE = 0 NCS Don't care 16 17 Data n HIZ MISO HIZ (Pull-Up) Don't care Data 1 MSB first Data 2 Init Addr.(5:0) MSB first SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MOSI 0 1 SCLK Data 1 MSB first Data 2 16 17 Data n Don't care MISO HIZ (Pull-Up) Don't care NCS 2 Init Addr.(5:0) MSB first 3 4 5 6 7 8 9 10 11 12 Figure 10: SPI read and write commands |
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