IC-HT datasheet(33/42 Pages) ICHAUS

33 / 42 page

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iC-HT

DUAL CW LASER DIODE DRIVER

Rev A1, Page 33/42

The register map consists of 64 addresses subdivided

in three different pages:

• Read-only page, addr. 0x00 to 0x0F: iC-HT sta-

tus, ADC readouts, thermometer readout and

chip revision.

• Conﬁguration page (integrity monitored), read-

write registers, addr. 0x10 to 0x1F.

• Validation page, read-write registers, addr. 0x30

to 0x3F.

Read-only registers

Read-only registers are sub-divided as well into sta-

tus registers (addr. 0x00 to 0x01) and measurement

registers. Status registers are normally latched to 1

on events and cleared on read (see individual regis-

ter description). Measurement registers are dual-port

and can be accessed simultaneously with the mea-

surements in progress. ADC1(addr. 0x03 to 0x04) and

ADC2 (addr. 0x05 to 0x06) are 10 bit registers split

into two 8 bit registers each and must be accessed in

block mode (automatic address increment) to ensure

data not changing during the read.

Conﬁguration page (integrity monitored)

The conﬁguration page (addr. 0x10 to 0x1F) contains

the registers that control the driver. Every write opera-

tion to any of the registers of this page will be internally

duplicated to the correspondent register at the valida-

tion page. After the write operation, the correspondent

validation register will contain the inverted value of the

conﬁguration register.

Validation page

The validation page (addr. 0x30 to 0x3F) can be read

or written normally. Only when a write procedure is

made to any of the conﬁguration registers the corre-

spondent validation pair will be written with the inverted

value of the conﬁguration register as well.

Both the conﬁguration and validation pages are initial-

ized during power-up. This event is signaled at the

STATUS0 register (bit 0, INITRAM). In standby mode

(NSTBY = lo) the RAM is not reset if any write com-

mand has been executed and therefore, conﬁguration

and validation pages keep the stored information and

INITRAM remains unset. Entering standby mode af-

ter power-up without any write command, the RAM

will be initialized again and the INITRAM bit will be

set to 1 again. Any VDD power-down event signaled

at the STATUS0 register outside the standby mode

(NSTBY = hi) requires a RAM content check regard-

less of the state of the INITRAM bit to ensure data is

not corrupted.

Possible start-up sequence:

1. iC-HT starts in operation mode with default con-

ﬁguration.

INITRAM and PDOVDD error bits

must be set in STATUS0, DISC1 (addr. 0x10, bit

3) and DISC2 (addr. 0x15, bit 3) are set to 1.

2. Write MODE(1:0) = "10" register (Addr. 0x1C) to

enable the conﬁguration mode.

3. Conﬁgure the laser channels.

4. Read back to verify a correct data transfer.

5. Set the DISC1, DISC2 bits to 0 on used chan-

nels.

6. Read the status registers(addr.

0x00, 0x01,

0x02) to detect possible errors and validate sta-

tus. If any error exist, read again to ensure its

validation.

7. Write MODE(1:0) = "01" register (addr. 0x1C) to

apply the conﬁguration and enable the memory

integrity check.

8. During operation: monitor the status registers

checking for errors. The NCHK pin signals any

set status bit if not masked. This pin can be used

to trigger an microcontroller interrupt line.

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