IC-HT datasheet(32/42 Pages) ICHAUS

32 / 42 page

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iC-HT

DUAL CW LASER DIODE DRIVER

Rev A1, Page 32/42

DIGITAL INTERFACE AND MEMORY INTEGRITY MONITOR

iC-HT provides a microcontroller slave interface by se-

lection on the EMC pin. iC-HT support the interfaces

SPI or I²C that are selected by the INS/WKR pin.

EMC

Addr. Pin;

iC-WK-mode, digital interfaces disabled

Open

Not allowed, error signaled

MCU mode, interface selected by INS/WKR

enabled

Table 64: Enable microcontroller

INS/WKR

Addr. Pin;

SPI interface selected

Open

Not allowed, error signaled.

I²C interface selected

Table 65: Interface selection I²C or SPI

The conﬁguration memory is integrity monitored and

atomic executable (all at once: changes of the conﬁg-

urations without any direct effects, the changes are ex-

ecuted at once by command ) to the functional blocks

of iC-HT.

Integrity monitoring is implemented by a duplication of

the conﬁguration registers into a validation page (see

description below) where the register are automatically

copied with inverted value. Every register bit is com-

pared with its validation copy and in case of difference,

a memory error is generated and both laser channels

are switched off.

Atomic appliance is achieved by latching the conﬁgu-

ration registers. This permits a full conﬁguration (differ-

ent registers) to be made prior to apply it to the laser

channels. iC-HT has two different modes selectable by

the MODE(1:0) register (addr. 0x1C).

MODE(1:0)

Addr. 0x1C; bit 1:0

R/W 01

Invalid parameter

Operation mode

Conﬁguration mode

Invalid parameter

Table 66: Conﬁguration and operation mode

In Conﬁguration mode, the conﬁguration memory

(addr. 0x10 to 0x1F) can be written and read back to

check a correct communication without changing the

present conﬁgured operation state of the iC-HT. In this

mode, the memory integrity check is disabled.

iC-HT will monitor the time elapsed in conﬁguration

mode and automatically switch the laser off if it ex-

ceeds a conﬁguration mode timeout. The time in con-

ﬁguration mode must less than 40 ms for ensuring that

no conﬁguration timeout occurs during conﬁguration

(cf. Electrical Characteristics No. E02). The timeout

can be up to 164 ms.

When writing the conﬁguration is completed, iC-HT is

switched to operation mode by writing "10" into the

MODE register (addr. 0x1C). In operation mode the

conﬁguration is applied to the iC-HT and the memory

integrity check activated. In this mode conﬁguration

registers can only be read (except MODE(1:0) regis-

ter, which is always accessible). Figure 18 shows the

interface to memory stucture.

RNW

RNW_RAM

MEMERR

LATCH

CFG(127:0)

CHECK

ERROR

DB(7:0)

RAM

Addr.

Decoder

RNW_VAL

VALIDATION

SPI / I2C

Addr. 0x1C

0x10

0x1F

MODE

0x30

0x3F

ADR(6:0)

Figure 18: Interface, RAM integrity monitoring and conﬁguration latching

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