TAS5706APAPR datasheet(7/71 Pages) TI1

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TAS5706A

TAS5706B

www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009

PIN FUNCTIONS (continued)

TYPE

5-V

TERMINATION

DESCRIPTION

(1)

TOLERANT

(2)

NAME

NO.

BST_A

High-side bootstrap supply for half-bridge A

BST_B

High-side bootstrap supply for half-bridge B

BST_C

High-side bootstrap supply for half-bridge C

BST_D

High-side bootstrap supply for half-bridge D

BYPASS

Nominally equal to VCC/8. Internal reference voltage for analog cells

15,

DVDD

3.3-V digital power supply

20,

DVSS

Digital ground

HPL_PWM

Headphone left-channel PWM output.

HPR_PWM

Headphone right-channel PWM output.

Headphone select, active high. When a logic HIGH is applied, device

enters headphone mode and speakers are HARD MUTED. When a

HPSEL

5-V

logic LOW is applied, device is in speaker mode and headphone

outputs become line outputs or are disabled.

LRCLK

5-V

Input serial audio data left/right clock (sampling rate clock)

MCLK is the clock master input. The input frequency of this clock can

MCLK

5-V

range from 4.9 MHz to 49 MHz.

Performs a soft mute of outputs, active-low. A logic low on this

terminal sets the outputs equal to 50% duty cycle. A logic high on this

MUTE

5-V

Pullup

terminal allows normal operation. The mute control provides a

noiseless volume ramp to silence. Releasing mute provides a

noiseless ramp to previous volume.

OSC_RES

Oscillator trim resistor. Connect an 18.2-k

Ω resistor to GND.

OUT_A

4, 5

Output, half-bridge A

OUT_B

1, 64

Output, half-bridge B

49,

OUT_C

Output, half-bridge C

45,

OUT_D

Output, half-bridge D

Power down, active-low. PDN powers down all logic, stops all clocks,

and outputs stops switching. When PDN is released, the device

PDN

5-V

Pullup

powers up all logic, starts all clocks, and performs a soft start that

returns to the previous configuration determined by register settings.

PGND_A

6, 7

Power ground for half-bridge A

PGND_B

2, 3

Power ground for half-bridge B

47,

PGND_C

Power ground for half-bridge C

43,

PGND_D

Power ground for half-bridge D

PLL_FLTM

PLL negative input

PLL_FLTP

PLL positive input

PVCC_A

8, 9

Power supply input for half-bridge output A

62,

PVCC_B

Power supply input for half-bridge output B

51,

PVCC_C

Power supply input for half-bridge output C

41,

PVCC_D

Power supply input for half-bridge output D

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TAS5706A is Not Recommended for New Designs

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