TAS5706APAPR datasheet(47/71 Pages) TI1

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SOFT MUTE REGISTER (0x06)

TAS5706A

TAS5706B

www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009

Bit D3 defines which volume register is used to control the volume of the HP_PWMx outputs when in headphone

mode. When set to 0, the HP volume register (0x0C) controls the volume of the headphone outputs when in

headphone mode. When bit D3 is set to 1, the channel volume registers (0x08–0x0B, 0x0D) are used for all

modes (line out, headphone, speaker).

Bits D2–D1 define the output modes. The default is speaker mode with the headphone mode selectable via the

external HPSEL terminal. The device can also be forced into headphone mode by asserting bit D1 (all other

PWM channels are muted). Asserting bit D2 puts the device into a pseudo-line-out mode where the HP_PWMx

and all other PWM channels are active. Bit D3 must also be asserted in this mode, and the HP_PWMx volume is

controlled with the main speaker output volume controls via registers 0x08–0x0B and 0x0D..

Table 8. System Control Register 2 (0x05)

FUNCTION

–

Reserved (1)

–

All channels are shut down (hard mute). VALID1 = 0.

–

All channels are shut down (hard mute). VALID1 = 0 (2)

When D6 is deasserted, all channels not belonging to shutdown group (SDG) are started.

–

SDG register is 0x19.

–

When D6 is deasserted, all channels are started. VALID1 = 1. No channels in SDG1.

–

Reserved (2)

Use HP volume register (0x0C) for adjusting headphone volume when in

–

headphone mode. (2)

–

Use channel volume registers (0x08–0x0B, 0x0D) for all modes.

–

Speaker mode. Hardware pin, HPSEL = 1, forces device into headphone mode. (2)

–

HP mode. This setting is logically ORed with external HPSEL pin.

Line out mode. Hardware pin, HPSEL, is ignored for this setting. HP_PWMx pins are

–

active.

–

Reserved

–

Reserved (2)

(1)

Default values are in bold.

(2)

Default values are in bold.

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle. Default is

0x00.

Table 9. Soft Mute Register (0x06)

FUNCTION

–

Soft mute channel 1

–

Soft mute channel 2

–

Soft mute channel 3

–

Soft mute channel 4

–

Soft mute subwoofer channel (channel 6)

Unmute all channels (1)

(1)

Default values are in bold.

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