PCF8576DTSLASH2 datasheet(33/57 Pages) NXP

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PCF8576D

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Product data sheet

Rev. 14 — 10 June 2013

33 of 57

NXP Semiconductors

PCF8576D

Universal LCD driver for low multiplex rates

11. Static characteristics

[1]

VLCD > 3 V for 1⁄3 bias.

[2]

LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.

[3]

The I2C-bus interface of PCF8576D is 5 V tolerant.

[4]

When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 18.

[5]

Propagation delay of driver between clock (CLK) and LCD driving signals.

[6]

Periodically sampled, not 100 % tested.

[7]

Outputs measured one at a time.

Table 19.

Static characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

VDD

supply voltage

1.8

5.5

VLCD

LCD supply voltage

[1]

2.5

6.5

IDD

supply current

fclk(ext) = 1536 Hz

[2]

-3.5

A

VDD =3.0 V;

Tamb =25 C

-2.7

A

IDD(LCD)

LCD supply current

fclk(ext) = 1536 Hz

[2]

-18

A

VDD(LCD) =3.0 V;

Tamb =25 C

-13

A

Logic[3]

VP(POR)

power-on reset supply voltage

1.0

1.3

1.6

VIL

LOW-level input voltage

on pins CLK, SYNC,

OSC, A0 to A2, SA0,

SCL, SDA

VSS

-0.3VDD

VIH

HIGH-level input voltage

on pins CLK, SYNC,

OSC, A0 to A2, SA0,

SCL, SDA

[4][5]

0.7VDD

-VDD

IOL

LOW-level output current

output sink current;

VOL = 0.4 V; VDD =5 V

on pins CLK and SYNC

on pin SDA

IOH(CLK)

HIGH-level output current on pin CLK

output source current;

VOH =4.6 V; VDD =5V

leakage current

VI =VDD or VSS;

on pins CLK, SCL, SDA,

A0 to A2 and SA0

1-

A

IL(OSC)

leakage current on pin OSC

VI =VDD

1-

A

input capacitance

[6]

LCD outputs

V

output voltage variation

on pins BP0 to BP3 and

S0 to S39

100

+100

output resistance

VLCD = 5 V

[7]

on pins BP0 to BP3

1.5



on pins S0 to S39

6.0



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