PCF8576DTSLASH2 datasheet(17/57 Pages) NXP

17 / 57 page

PCF8576D

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Product data sheet

Rev. 14 — 10 June 2013

17 of 57

NXP Semiconductors

PCF8576D

Universal LCD driver for low multiplex rates

7.5 Oscillator

7.5.1 Internal clock

The internal logic of the PCF8576D and its LCD drive signals are timed either by its

internal oscillator or by an external clock. The internal oscillator is enabled by connecting

pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used

as the clock signal for several PCF8576Ds in the system that are connected in cascade.

7.5.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD

frame signal frequency is determined by the clock frequency (fclk).

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing

The PCF8576D timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each PCF8576D in the system is

maintained by the synchronization signal at pin SYNC. The timing also generates the LCD

frame signal whose frequency is derived from the clock frequency. The frame signal

frequency is a fixed division of the clock frequency from either the internal or an external

clock:

7.7 Display register

The display latch holds the display data while the corresponding multiplex signals are

generated.

7.8 Segment outputs

The LCD drive section includes 40 segment outputs S0 to S39 which should be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display latch. When

less than 40 segment outputs are required, the unused segment outputs should be left

open-circuit.

clk

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