PCF8576DTSLASH2 datasheet(18/57 Pages) NXP

18 / 57 page

PCF8576D

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Product data sheet

Rev. 14 — 10 June 2013

18 of 57

NXP Semiconductors

PCF8576D

Universal LCD driver for low multiplex rates

7.9 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required, the

unused outputs can be left open-circuit.

• In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 all carry the

same signals and may also be paired to increase the drive capabilities.

• In static drive mode the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

7.10 Display RAM

The display RAM is a static 40

 4-bit RAM which stores LCD data.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bit map, Figure 12, shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the

segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,

second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,

and BP3 respectively.

When display data is transmitted to the PCF8576D, the received display bytes are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and depending on the current multiplex drive mode the bits are stored singularly,

The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs; and between the bits in a RAM row and the backplane outputs.

Fig 12. Display RAM bit map

display RAM addresses (columns)/segment outputs (S)

display RAM bits

(rows)/

backplane outputs

(BP)

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