LP3906 datasheet(24/47 Pages) TI

24 / 47 page

ADR6

bit7

MSB

ADR5

bit6

ADR4

bit5

ADR3

2C SLAVE address (chip address)

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

LSB

bit4

SDA

SCL

START condition

STO

P condition

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LP3906

SNVS456M – AUGUST 2006 – REVISED MAY 2013

www.ti.com

I2C DATA VALIDITY

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), e.g.- the state of the

data line can only be changed when CLK is LOW.

Figure 34. I2C Signals: Data Validity

I2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as the

SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while the SCL is HIGH. The I2C master always generates START and STOP

bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

Figure 35. START and STOP Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying acknowledgement. A receiver which has been

addressed must generate an acknowledgement (“ACK”) after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). Please note that according to industry I2C standards for 7-bit

addresses, the MSB of an 8-bit address is removed, and communication actually starts with the 7th most

significant bit. For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte

selects the register to which the data will be written. The third byte contains data to write to the selected register.

LP3906 has a chip address of 60’h, which is factory programmed.

Figure 36. I2C Chip Address

Submit Documentation Feedback

Product Folder Links: LP3906

LP3906 датащи(PDF) 24 Page - Texas Instruments

LP3906 датащи(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

датащи скачать

ссылки URL