LP3906 datasheet(23/47 Pages) TI

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EN_T

Vout Buck1

Vout Buck2

Vout LDO1

Vout LDO2

LP3906

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SNVS456M – AUGUST 2006 – REVISED MAY 2013

NOTE

LP3906 The default Power on delays can be reprogrammed at final test or I2C to 1, 1.5, 2,

3, 6, or 11 ms.

LP3906 Default Power-Off Sequence

Symbol

Description

Min

Typ

Max

Units

Programmable Delay from EN_T deassertion to VCC_Buck1 Off

1.5

Programmable Delay from EN_T deassertion to VCC_Buck2 Off

Programmable Delay from EN_T deassertion to VCC_LDO1 Off

Programmable Delay from EN_T deassertion to VCC_LDO2 Off

NOTE

LP3906 The default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or

10 ms. Default setting is the same as the on sequence.

Power-On-Reset

The LP3906 is equipped with an internal Power-On-Reset (“POR”) circuit that will reset the logic when VDD <

VPOR. This ensures that the logic is properly initialized when VDD rises above the minimum operating voltage of

the Logic and the internal oscillator that clocks the Sequential Logic in the Control section.

2C Compatible Serial Interface

I2C SIGNALS

The LP3906 features an I2C compatible serial interface, using two dedicated pins: SCL and SDA for I2C clock

and data respectively. Both signals need a pull-up resistor according to the I2C specification. The LP3906

interface is an I2C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400 kbit/s. See

I2C specification from Philips for further details.

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