LP3906

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SNVS456M – AUGUST 2006 – REVISED MAY 2013

Pin Name

Pin No.

I/O

Type

Description

VIN2

1

I

PWR

Power in from either DC source or Battery to Buck 2

SW2

2

O

PWR

Buck2 switcher output pin

GND_SW2

3

G

G

Buck2 NMOS Power Ground

GND_C

4

G

G

Non switching core ground pin

GND_SW1

5

G

G

Buck1 NMOS Power Ground

SW1

6

O

PWR

Buck1 switcher output pin

VIN1

7

I

PWR

Power in from either DC source or Battery to buck 1

SDA

8

I/O

D

SCL

9

I

D

EN_T

10

I

D

Enable for preset power on sequence.

FB1

11

I

A

Buck1 input feedback terminal

AVDD

12

I

PWR

Analog Power for Buck converters.

VINLDO1

13

I

PWR

Power in from either DC source or Battery to input terminal of LDO1

LDO1

14

O

PWR

LDO1 Output

ENLDO1

15

I

D

LDO1 enable pin, a logic HIGH enables the LDO1

ENLDO2

16

I

D

LDO2 enable pin, a logic HIGH enables the LDO2

GND_L

17

G

G

LDO Ground

LDO2

18

O

PWR

LDO2 Output

VINLDO2

19

I

PWR

Power in from either DC source or battery to input terminal to LDO2

VinLDO12

20

I

PWR

Analog Power for Internal Functions (VREF, BIAS, I2C, Logic)

FB2

21

I

A

Buck2 input feedback terminal

ENSW1

22

I

D

Enable Pin for Buck1 switcher, a logic HIGH enables Buck1

SYNC

23

I

D

Frequency Synchronization pin which allows the user to connect an external

clock signal PLL to synchronize the PMIC internal oscillator.

ENSW2

24

I

D

Enable Pin for Buck2 switcher, a logic HIGH enables Buck2

DAP

DAP

GND

GND

Connection isn't necessary for electrical performance, but it is recommended

for better thermal dissipation.

(1)

A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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