DS32EL0421, DS32ELX0421

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SNLS282F – MAY 2008 – REVISED APRIL 2013

Table 2. Device Configuration Table

Remote Sense Pin

DC-Balance Pin (DC_B)

Configuration

(RS)

0

0

Remote Sense enabled

DC-Balance enabled

Data Alignment

Scrambler and NRZI encoder disabled by default

0

1

Remote Sense enabled

DC-Balance disabled

Data Alignment

Scrambler and NRZI encoder enabled by default

1

0

Remote Sense disabled

DC-Balance enabled

Data Alignment

Scrambler and NRZI encoder enabled by default

1

1

Remote Sense disabled

DC-Balance disabled

No Data Alignment

Scrambler and NRZI encoder disabled by default

SMBus INTERFACE

The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the

Chip Select signal is required. Holding the SMB_CS pin HIGH enables the SMBus port, allowing access to the

configuration registers. Holding the SMB_CS pin LOW disables the device's SMBus, allowing communication

from the host to other slave devices on the bus. In the STANDBY state, the System Management Bus remains

active. When communication to other devices on the SMBus is active, the SMB_CS signal for the serializer must

be driven LOW.

The address byte for all DS32EL0421 and DS32ELX0421 devices is AE'h. Based on the SMBus 2.0

specification, these devices have a 7-bit slave address of 1010111'b. The LSB is set to 0'b (for a WRITE), thus

the 8-bit value is 1010 1110 'b or AE'h.

The SCK and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low

impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not

5V tolerant.

Transfer of Data via the SMBus

During normal operation the data on SDA must be stable during the time when SCK is HIGH.

There are three unique states for the SMBus:

START

A HIGH to LOW transition on SDA while SCK is HIGH indicates a message START condition

STOP

A LOW to HIGH transition on SDA while SCK is HIGH indicates a message STOP condition.

IDLE

SMBus Transactions

The devices support WRITE and READ transactions. See Register Description Table for register address, type

(Read/ Write, Read Only), default value and function information.

Writing to a Register

To write a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host (Master) selects the device by driving its SMBus Chip Select (SMB_CS) signal HIGH.

2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.

3. The Device (Slave) drives the ACK bit (“0”).

4. The Host drives the 8-bit Register Address.

5. The Device drives an ACK bit (“0”).

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Product Folder Links: DS32EL0421 DS32ELX0421