DS32EL0421, DS32ELX0421

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SNLS282F – MAY 2008 – REVISED APRIL 2013

DS32EL0421 , DS32ELX0421 125 - 312.5 MHz FPGA-Link Serializer with DDR LVDS

Parallel Interface

Check for Samples: DS32EL0421, DS32ELX0421

1

FEATURES

DESCRIPTION

The DS32EL0421/DS32ELX0421 is a 125 MHz to

2

•

5-bit DDR LVDS Parallel Data Interface

312.5 MHz (DDR) serializer for high-speed serial

•

Programmable Transmit De-emphasis

transmission

over

FR-4

printed

circuit

board

•

backplanes, balanced cables, and optical fiber. This

easy-to-use chipset integrates advanced signal and

•

Selectable DC-balanced Encoder

clock conditioning functions, with an FPGA friendly

•

Selectable Data Scrambler

interface.

•

Remote Sense for Automatic Detection and

The DS32EL0421/DS32ELX0421 serializes up to 5

Negotiation of Link Status

parallel input LVDS channels to create a maximum

•

On Chip LC VCOs

data payload of 3.125 Gbps. If the integrated DC-

•

Redundant Serial Output (ELX device only)

balance encoding is enabled, the maximum data

payload achievable is 2.5 Gbps.

•

Data Valid Signaling to Assist with

Synchronization of Multiple Receivers

The DS32EL0421/DS32ELX0421 serializers feature

remote sense capability to automatically detect and

•

Supports AC- and DC-coupled Signaling

negotiate

link

status

with

its

companion

•

Integrated CML and LVDS Terminations

DS32EL0124/DS32ELX0124

deserializers

without

•

Configurable PLL Loop Bandwidth

requiring an additional feedback path.

•

Programmable Output Termination (50

Ω or

The parallel LVDS interface reduces FPGA I/O pins,

75

Ω).

board trace count and alleviates EMI issues, when

•

Built-in Test Pattern Generator

compared

to

traditional

single-ended

wide

bus

interfaces.

•

Loss of Lock and Error Reporting

•

Configurable via SMBus

The DS32EL0421/DS32ELX0421 is programmable

through a SMBus interface as well as through control

•

48-pin WQFN Package with Exposed DAP

pins.

TARGET APPLICATIONS

•

Imaging: Industrial, Medical Security, Printers

•

Displays: LED Walls, Commercial

•

Video Transport

•

Communication Systems

•

Test and Measurement

•

Industrial Bus

KEY SPECIFICATIONS

•

1.25 to 3.125 Gbps Serial Data Rate

•

125 to 312.5 MHz DDR Parallel Clock

•

-40° to +85°C Temperature Range

•

>8 kV ESD (HBM) Protection

•

Low Intrinsic Jitter — 35ps at 3.125 Gbps

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2

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PRODUCTION DATA information is current as of publication date.

Copyright © 2008–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.