DS32ELX0421

TXIN4

SDA

SCK

SMB_CS

GPIO2

2.5V

3.3V

VDDPLL

LF_REF

LF_CP

100 nF

GPIO0

GPIO1

22 PF

3.3V

TXOUT0

TXOUT1

+

-

+

-

VOD_CTRL

9.1 k:

1, 36

7, 15, 18,

25, 35

49

16

17

19

20

28

48

47

14

27

26

3

4

11

32

33

34

3.3V

3.3V

0.1 PF

0.1 PF

6

5

1.5 k:

1:

LOCK

31

RESET

30

TXIN3

+

-

43

45

TXIN2

+

-

44

46

TXIN1

+

-

42

41

TXIN0

+

-

40

39

TXCLKIN

+

-

38

37

+

-

DS32EL0421, DS32ELX0421

www.ti.com

SNLS282F – MAY 2008 – REVISED APRIL 2013

LINK AGGREGATION

Multiple

DS32EL0421/DS32ELX0421

serializers

and

D32EL0124/DS32ELX0124

deserializers

can

be

aggregated together if an application requires a data throughput of more than 3.125 Gbps. By utilizing the data

valid signal of each device, the system can be properly deskewed to allow for a single cable, such as CAT-6,

DVI-D, or HDMI, to carry data payloads beyond 3.125 Gbps.

Link aggregation configurations can also be implemented in applications which require longer cable lengths. In

these type of applications the data rate of each serializer and deserializer chipset can be reduced, such that the

applications' net data throughput is still the same. Since each high speed channel is now operating at a fraction

of the original data rate, the loss over the cable is reduced, allowing for greater lengths of cable to be used in the

system.

For more information regarding link aggregation please see SNLA109, Expanding the Payload with TI's FPGA-

Link DS32ELX0421 and DS32ELX0124 Serializer and Deserializer.

LAYOUT GUIDELINES

It is important to follow good layout practices for high speed devices. The length of LVDS input traces should not

exceed 40 inches. In noisy environment the LVDS traces may need to be shorter to prevent data corruption due

to EMI. Noisy components should not be placed next to the LVDS or CML traces. The LVDS and CML traces

must have a controlled differential impedance of 100

Ω. Do not place termination resistor at the LVDS inputs or

CML outputs, the DS32EL0421 and DS32ELX0421 have internal termination resistors. It is recommended to

avoid using vias. Vias create an impedance mismatch in the transmission line and result in reflections, which can

greatly lower the maximum distance of the high speed data link. If vias are required, they should be placed

symmetrically on each side of the differential pair. For more tips and detailed suggestions regarding high speed

board layout principles, please consult the LVDS Owner’s Manual.

Figure 11. Typical Interface Circuit

Copyright © 2008–2013, Texas Instruments Incorporated

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