DS32EL0421 datasheet(23/32 Pages) TI1

23 / 32 page

DS32EL0421, DS32ELX0421

www.ti.com

SNLS282F – MAY 2008 – REVISED APRIL 2013

Addr

Name

Bits

Field

R/W

Default

Description

(Hex)

Power Down

Channel Reset

R/W

1: Reset high speed channel. Self-clearing bit.

Clock Powerdown

R/W

1: Power down parallel, parallel-to-serial, and always on

clock

LVDS Clock

R/W

1'b

0: Disable TxCLKIN

enable

1: Enable TxCLKIN

TxIN4 Enable

R/W

1'b

0: Disable TxIN4

1: Enable TxIN4

TxIN3 Enable

R/W

1'b

0: Disable TxIN3

1: Enable TxIN3

TxIN2 Enable

R/W

1'b

0: Disable TxIN2

1: Enable TxIN2

TxIN1 Enable

R/W

1'b

0: Disable TxIN1

1: Enable TxIN1

TxIN0 Enable

R/W

1'b

0: Disable TxIN0

1: Enable TxIN0

Event Disable

7:5

Reserved

R/W

PLL Lock Disable

R/W

0: Count clock errors

1: Clock error count disabled

FIFO Error

R/W

0: Count FIFO erros 1: FIFO error count disabled

Disable

Parallel Clock

R/W

0: Count clock detect errors

Detect Disable

1: Clock detect count disabled

Clock Loss of

R/W

0: Count clock los of signal errors

Signal Disable

1: Clock loss of signal count disabled

Data Loss of

R/W

0: Count data los of signal errors

Signal Disable

1: Clock data of signal count disabled

LVDS Operation

7:2

Reserved

LVDS Loss of

R/W

1: Preset signal for LVDS loss of signal register

Signal Preset

LVDS Loss of

R/W

1: Clear signal for LVDS loss of signal register

Signal Reset

Loss of Signal

7:6

Reserved

Status

Clock Loss of

0: Clock present

Signal

1: No clock present on TxCLKIN

4:0

Data Loss of

0: Data present

Signal

1: No data present on TxIN4:0

Event Status

7:4

Reserved

TxCLKIN Detect

R/W

0: TxCLKIN not detected

1: TxCLKIN detected

Reserved

1:0

Link Detect 1:0

R/W

0: Link not detected

1: Link detected

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