ADAS1000BSTZ datasheet(16/80 Pages) AD

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ADAS1000/ADAS1000-1/ADAS1000-2

Data Sheet

Rev. A | Page 16 of 80

ADAS1000

ADAS1000-1

ADAS1000-2

Mnemonic

Description

LQFP

LFCSP

LQFP

LFCSP

ECG5_V2

Analog Input, Chest Electrode 2 or Auxiliary Biopotential Input (V2).

ECG1

Analog Input 1.

ECG2

Analog Input 2.

ECG3

Analog Input 3.

ECG4

Analog Input 4.

ECG5

Analog Input 5.

EXT_RESP_RA

Optional External Respiration Input.

EXT_RESP_LL

Optional External Respiration Input.

EXT_RESP_LA

Optional External Respiration Input.

RESPDAC_LL

Optional path for higher performance respiration resolution, respiration

DAC drive, Negative Side 0.

SHIELD/

RESPDAC_LA

Shared Pin (User-Configured).

Output of Shield Driver (SHIELD).

Optional Path for Higher Performance Respiration Resolution, Respiration

DAC Drive, Negative Side 1 (RESPDAC_LA).

RESPDAC_RA

Optional Path for Higher Performance Respiration Resolution, Respiration

DAC Drive, Positive Side.

CM_OUT/WCT

Common-Mode Output Voltage (Average of Selected Electrodes). Not

intended to drive current.

CM_IN

Common-Mode Input.

RLD_SJ

Summing Junction for Right Leg Drive Amplifier.

RLD_OUT

Output and Feedback Junction for Right Leg Drive Amplifier.

CAL_DAC_IO

Calibration DAC Input/Output. Output for a master device, input for a

slave. Not intended to drive current.

REFIN

Reference Input. For standalone mode, use REFOUT connected to REFIN.

External 10 μF with ESR < 0.2 Ω in parallel with 0.1 μF bypass capacitors to

GND are required and should be placed as close to the pin as possible. An

external reference can be connected to REFIN.

REFOUT

Reference Output.

REFGND

Reference Ground. Connect to a clean ground.

27, 28

47, 46

XTAL1, XTAL2

External crystal connects between these two pins; external clock drive

should be applied to CLK_IO. Each XTAL pin requires 15 pF to ground.

CLK_IO

Buffered Clock Input/Output. Output for a master device; input for a slave.

Powers up in high impedance.

Chip Select and Frame Sync, Active Low. CS can be used to frame each

word or to frame the entire suite of data in framing mode.

SCLK

Clock Input. Data is clocked into the shift register on a rising edge and

clocked out on a falling edge.

SDI

Serial Data Input.

Power-Down, Active Low.

SDO

Serial Data Output. This pin is used for reading back register configuration

data and for the data frames.

DRDY

Digital Output. This pin indicates that conversion data is ready to be read

back when low, busy when high. When reading packet data, the entire

packet must be read to allow DRDY to return high.

RESET

Digital Input. This pin has an internal pull-up. This pin resets all internal

nodes to their power-on reset values.

SYNC_GANG

Digital Input/Output (Output on Master, Input on Slave). Used for

synchronization control where multiple devices are connected together.

Powers up in high impedance.

GPIO0/MCS

General-Purpose I/O or Master 128 kHz SPI CS.

GPIO1/MSCLK

General-Purpose I/O or Master 128 kHz SPI SCLK.

GPIO2/MSDO

General-Purpose I/O or Master 128 kHz SPI SDO.

GPIO3

General-Purpose I/O.

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