поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

ADAS1000BSTZ датащи(PDF) 73 Page - Analog Devices

номер детали ADAS1000BSTZ
подробное описание детали  Low Power, Five Electrode trocardiogram (ECG) Analog Front End
PDF  80 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADAS1000BSTZ датащи(HTML) 73 Page - Analog Devices

Back Button ADAS1000BSTZ Datasheet HTML 69Page - Analog Devices ADAS1000BSTZ Datasheet HTML 70Page - Analog Devices ADAS1000BSTZ Datasheet HTML 71Page - Analog Devices ADAS1000BSTZ Datasheet HTML 72Page - Analog Devices ADAS1000BSTZ Datasheet HTML 73Page - Analog Devices ADAS1000BSTZ Datasheet HTML 74Page - Analog Devices ADAS1000BSTZ Datasheet HTML 75Page - Analog Devices ADAS1000BSTZ Datasheet HTML 76Page - Analog Devices ADAS1000BSTZ Datasheet HTML 77Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 73 / 80 page
background image
Data Sheet
ADAS1000/ADAS1000-1/ADAS1000-2
Rev. A | Page 73 of 80
Example 4: Configure 150 Hz Test Tone Sine Wave on
Each ECG Channel and Stream Conversion Data
1. Write 1 configures the CMREFCTL register to VCM_REF
= 1.3 V (no electrodes contribute to VCM). RLD is enabled
to RLD_OUT, and the shield amplifier enabled.
2. Write 2 addresses the TESTTONE register to enable the
150 Hz sine wave onto all electrode channels.
3. Write 3 addresses the FILTCTL register to change the
internal low-pass filter to 250 Hz to ensure that the 150 Hz
sine wave can pass through.
4. Write 4 configures the FRMCTL register to output nine
words per frame/packet. The frame/packet of words
consists of the header and five ECG words, pace,
respiration magnitude, and lead-off. The frame is
configured to always send, irrespective of ready status. The
ADAS1000 is in electrode format mode with a data rate of
2 kHz. Electrode format is required to see the test tone
signal correctly on each electrode channel.
5. Write 5 addresses the ECGCTL register, enabling all
channels into a gain of 1.4, low noise mode. It configures
the device as a master and driven from the XTAL input
source. The ADAS1000 is also put into conversion mode
in this write.
6. Write 6 issues the read command to start putting the
converted data out on the SDO pin.
7. Continue to issue SCLK cycles to read the converted data
at the configured packet data rate.
Example 5: Enable Pace Detection and Stream
Conversion Data
1. Write 1 configures the PACECTL register with all three
pace detection instances enabled, PACE1EN detecting on
Lead II, PACE2EN detecting on Lead I, and PACE3EN
detecting on Lead aVF. The pace width filter and validation
filters are also enabled.
2. Write 2 issues the read command to start putting the
converted data out on the SDO pin.
3. Continue to issue SCLK cycles to read the converted data
at the configured packet data rate. When a valid pace is
detected, the detection flags are confirmed in the header
word and the PACEDATA register contains information
on the width and height of the measured pulse from each
measured lead.
4. Note that the PACEAMPTH register default setting is
0x242424, setting the amplitude of each of the pace
instances to 1.98 mV/gain.
5. Note that this example assumes that the FRMCTL register
has already been configured such that the PACEDATA
word is available in the data frame, as arranged in Write 2
of Example 1.
Table 57. Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data
Write Command
Register Addressed
Read/Write Bit
Register Address
Data
32-Bit Write Command
Write 1
CMREFCTL
1
000 0101
0000 0000 0000 0000 0000 1011
0x8500000B
Write 2
TESTTONE
1
000 1000
1111 1000 0000 0000 0000 1101
0x88F8000D
Write 3
FILTCTL
1
000 1011
0000 0000 0000 0000 0000 1000
0x8B000008
Write 4
FRMCTL
1
000 1010
0000 0111 1001 0110 0001 0000
0x8A079610
Write 5
ECGCTL
1
000 0001
1111 1000 0000 0000 1010 1110
0x81F800AE
Write 6
FRAMES
0
100 0000
0000 0000 0000 0000 0000 0000
0x40000000
Table 58. Example 5: Enable Pace Detection and Stream Conversion Data
Write Command
Register Addressed
Read/Write Bit
Register Address
Data
32-Bit Write Command
Write 1
PACECTL
1
000 0100
0000 0000 0000 1111 1000 1111
0x84000F8F
Write 2
FRAMES
0
100 0000
0000 0000 0000 0000 0000 0000
0x40000000



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com