ADAS1000BSTZ datasheet(48/80 Pages) AD

48 / 80 page

ADAS1000/ADAS1000-1/ADAS1000-2

Data Sheet

Rev. A | Page 48 of 80

SERIAL INTERFACES

The ADAS1000/ADAS1000-1/ADAS1000-2 are controlled via

a standard serial interface allowing configuration of registers

and readback of ECG data. This is an SPI-compatible interface

that can operate at SCLK frequencies up to 40 MHz.

The ADAS1000/ADAS1000-1 also provide an optional

secondary serial interface that is capable of providing ECG data

at the 128 kHz data rate for users wishing to apply their own

digital pace detection algorithm. This is a master interface that

operates with an SCLK of 20.48 MHz.

STANDARD SERIAL INTERFACE

The standard serial interface is LVTTL-compatible when

operating from a 2.3 V to 3.6 V IOVDD supply. This is the

primary interface for controlling the ADAS1000/ADAS1000-1/

ADAS1000-2, reading and writing registers, and reading frame

data containing all the ECG data-words and other status

functions within the device.

The SPI is controlled by the following five pins:

•

CS (frame synchronization input). Asserting CS low

selects the device. When CS is high, data on the SDI

pin is ignored. If CS is inactive, the SDO output driver is

disabled, so that multiple SPI devices can share a common

SDO pin. The CS pin can be tied low to reduce the number

of isolated paths required. When CS is tied low, there is no

frame around the data-words; therefore, the user must be

aware of where they are within the frame. All data-words

with 2 kHz and 16 kHz data rates contain register addresses

at the start of each word within the frame. Users can

resynchronize the interface by holding SDI high for 64

SCLK cycles, followed by a read of any register so that SDI

is brought low for the first bit of the following word.

•

SDI (serial data input pin): Data on SDI is clocked into the

device on the rising edges of SCLK.

•

SCLK (clocks data in and out of the device). SCLK should

idle high when CS is high.

•

SDO (serial data output pin for data readback). Data is

shifted out on SDO on the falling edges of SCLK. The

SDO output driver is high-Z when CS is high.

•

DRDY (data ready, optional). Data ready when low,

busy when high. Indicates the internal status of the

ADAS1000/ADAS1000-1/ADAS1000-2 digital logic. It is

driven high/busy during reset. If data frames are enabled

and the frame buffer is empty, this pin is driven busy/high.

If the frame buffer is full, this pin is driven low/ready. If

data frames are not enabled, this pin is driven low to

indicate that the device is ready to accept register

read/write commands. When reading packet data, the

entire packet must be read to allow the DRDY return

back high.

Figure 76. Serial Interface

Write Mode

The serial word for a write is 32 bits long, MSB first. The

serial interface works with both a continuous and a burst

(gated) serial clock. The falling edge of CS starts the write

cycle. Serial data applied to SDI is clocked into the ADAS1000/

ADAS1000-1/ADAS1000-2 on rising SCLK edges. At least 32

rising clock edges must be applied to SCLK to clock in 32 bits of

data before CS is taken high again. The addressed input register

is updated on the rising edge of CS. For another serial transfer

to take place, CS must be taken low again. Register writes are

used to configure the device. Once the device is configured and

enabled for conversions, frame data can be initiated to start

clocking out ECG data on SDO at the programmed data rate.

Normal operation for the device is to send out frames of ECG

data. Typically, register reads and writes should be needed only

during start-up configuration. However, it is possible to write

new configuration data to the device while in framing mode.

A new write command is accepted within the frame and,

depending on the nature of the command, there may be a need

to flush out the internal filters (wait periods) before seeing

usable framing data again.

Write/Read Data Format

Address, data, and the read/write bits are all in the same word.

Data is updated on the rising edge of CS or the first cycle of the

following word. For all write commands to the ADAS1000/

ADAS1000-1/ADAS1000-2, the data-word is 32 bits, as shown

in Table 16. Similarly, when using data rates of 2 kHz and

16 kHz, each word is 32 bits (address bits and data bits).

Table 16. Serial Bit Assignment (Applies to All Register

Writes, 2 kHz and 16 kHz Reads)

B31

[B30:B24]

[B23:B0]

R/W

Address bits[6:0]

Data bits [23:0] (MSB first)

For register reads, data is shifted out during the next word, as

shown in Table 17.

Table 17. Read/Write Data Stream

Digital

Command 1

Command 2

SDI

Read Address 1

Read Address 2

Write Address 3

SDO

Address 1

Read Data 1

Address 2

Read Data 2

MICROCONTROLLER/

DSP

ADAS1000

SCLK

SDI

SDO

DRDY

SCLK

MOSI

MISO

GPIO

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