AM3703CUS datasheet(154/280 Pages) TI

154 / 280 page

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

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•

Bypass Mode

– RLOAD = 1.5 kΩ (±1%)

– RSET = 10 kΩ (±1%)

Table 5-3. DAC

—Static Electrical Specifications—Bypass Mode(2)

PARAMETER

CONDITIONS/ASSUMPTIONS

MIN

TYP

MAX

UNIT

Resolution

Bits

DC ACCURACY

INL(1)

Integral nonlinearity (INL)

37 to 954 input code range, RLOAD = 1.5 kΩ

–1

LSB

DNL(1)

Differential nonlinearity

37 to 954 input code range, RLOAD = 1.5 kΩ

–1

LSB

ANALOG OUTPUT

Output voltage

RLOAD = 1.5 kΩ

0.6

0.7

0.77

Output current

RLOAD = 1.5 kΩ

0.6

0.7

0.77

Gain error

–10

% FS

POWER CONSUMPTION

Ivdda-up

Analog supply current

Average current on vdda_dac, RLOAD = 1.5 kΩ

0.7

1.0

1.4

Input code 1023

Ivdda-down

Analog supply current, total

T = 30C

º, vdda_dac = 1.8 V, no load

μA

power down

Ivdda-stdby

Analog supply current,

Bandgap and internal LDO are ON, all other

180

270

μA

standby mode

analog blocks are OFF, no load, T = 30C

(1) In bypass mode, output node is cvideo1_out and cvideo2_out nodes. For more information, see Section 5.2, TVOUT Bypass Mode

(DAC Only) or Section 5.3, TVOUT Bypass Mode in Dual-Channel Configuration.

(2) For more information on code range definition, see Figure 5-4.

Table 5-4. Video DAC

—Dynamic Electrical Specifications—Bypass Mode

PARAMETER

CONDITIONS/ASSUMPTIONS

MIN

TYP

MAX

UNIT

fCLK

Output update rate

Equal to input clock frequency

MHz

Clock jitter

RMS clock jitter required in order to

assure 10-bit accuracy

Signal bandwidth

3dB

MHz

SFDR

Within bandwidth 1 kHz to 6 MHz

fCLK = 54 MHz, fOUT = 1 MHz, sine

wave input, 111 to 895 input code

range

SNR

Within bandwidth 1 kHz to 6 MHz

fCLK = 54 MHz, fOUT = 1 MHz, sine

wave input, 256 to 768 input code

range

PSR

Power supply rejection (up to 6 MHz)

100 mVpp at 6 MHz, input code 895

6(1)

(1) For more information on code range definition, see Figure 5-4.

5.6

Analog Supply (vdda_dac) Noise Requirements

In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the

noise requirements stated in this section.

The DAC Power Supply Rejection Ratio (PSRR) is defined as the relative variation of the full-scale output

current divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per

volt

supply

variation

shown

the

following

equation:

154

Video DAC Specifications

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