AM3703CUS datasheet(151/280 Pages) TI

151 / 280 page

AM3715, AM3703

www.ti.com

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

Table 5-1. DAC

– Static Electrical Specifications(8) (continued)

PARAMETER

CONDITIONS/ASSUMPTIONS

MIN

TYP

MAX

UNIT

POWER CONSUMPTION

Ivdda-up

Analog Supply

DC mode No

Average current on vdda_dac, no

4.5

6.5

8.5

Current(4)

load

load, 2 channels

Input code 50 (maximum output

AC mode No

voltage)

load

Full load 75-

load

Ivdda-up (peak)

Peak analog supply current

Lasts less than 1 ns

Ivdd-up

Digital supply current(5)

Average current, measured at fCLK

= 54 MHz,

fOUT = 2 MHz sine wave, vdd = 1.1

Ivdd-up (peak)

Peak digital supply current(6)

Peak current, full-scale transition

lasting less than 1 ns

Ivdda-down

(9)

Analog supply current, total power

T = 30

ºC, vdda_dac = 1.8 V, no

μA

down(9)

load

Ivdda-stdby

(9)

Analog supply current, standby mode(9)

Bandgap and internal LDO are ON,

180

270

μA

all other analog blocks are OFF, no

load, T = 30 C

Ivdd-down(pm)

(9)

Digital supply current, total power

T = 30

ºC, Full

Low-swing mode

μA

down(9)

or Partial Power

High-swing mode

Management

Ivdd-down(nopm)

Digital supply current, total power down

T = 30

ºC, VDD = 1.1 V, no Power

μA

(no power management)

Management

(1) The INL is measured at the output of the DAC (accessible at an external pin during bypass mode). The INL at code 783 equals 0.

(2) The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode). The INL at code 783 equals 0.

(3) Reference PSR measures the effect of a supply disturbance at cvideo1_out and cvideo2_out.

(4) The analog supply current Ivdda is directly proportional to the full-scale output current IFS and is insensitive to fCLK.

(5) The digital supply current IVDD is dependent on the digital input waveform, the DAC update rate fCLK, and the digital supply VDD.

(6) The peak digital supply current occurs at full-scale transition for duration less than 1 ns.

(7) See Section 5.6, Analog Supply (vdda_dac) Noise Requirements, for actual maximum ripple allowed on vdda_dac.

(8) For more information on code range definition, see Figure 5-4.

(9) For more information on AVDAC power-up, power-down, and standby mode configurations, see Display Subsystem / Display

Subsystem Functional Description / Video Encoder Functionalities / Video DAC Stage Power Management section of AM/DM37x

Technical Reference Manual (literature number SPRUGN4).

NOTE

High-swing mode is the default mode. The low-swing mode is not compliant with the NTSC

and PAL video-standards. It is used only for backwards compatibility to AM/DM37x.

Video DAC Specifications

151

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