LTC3404MPMS8 datasheet(13/16 Pages) LINER

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LTC3404

3404fb

APPLICATIO S I FOR ATIO

Figure 7. LTC3404 Layout Diagram

–

RUN

ITH

VFB

GND

PLL LPF

SYNC/MODE

LTC3404

CC2

CC1

COUT

3404 F07

VIN

BOLD LINES INDICATE

HIGH CURRENT PATHS

OPTIONAL

–

VOUT

VIN

CIN

which is below the maximum junction temperature of

125

°C.

Note that at higher supply voltages, the junction tempera-

ture is lower due to reduced switch resistance (RDS(ON)).

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, VOUT immediately shifts by an amount

equal to (

ΔILOAD • ESR), where ESR is the effective series

resistance of COUT. ΔILOAD also begins to charge or

discharge COUT, which generates a feedback error signal.

The regulator loop then acts to return VOUT to its steady-

state value. During this recovery time VOUT can be moni-

tored for overshoot or ringing that would indicate a stabil-

ity problem. The internal compensation provides adequate

compensation for most applications. But if additional

compensation is required, the ITH pin can be used for

external compensation using RC, CC1 as shown in

Figure 7. (The 47pF capacitor, CC2, is typically needed for

noise decoupling.)

A second, more severe transient is caused by switching in

loads with large (>1

μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

deliver enough current to prevent this problem if the load

switch resistance is low and it is driven quickly. The only

solution is to limit the rise time of the switch drive so that

the load rise time is limited to approximately (25 • CLOAD).

Thus, a 10

μF capacitor charging to 3.3V would require a

250

μs rise time, limiting the charging current to about

130mA.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3404. These items are also illustrated graphically in

the layout diagram of Figure 7. Check the following in your

layout:

1. Are the signal and power grounds segregated? The

LTC3404 signal ground consists of the resistive

divider, the optional compensation network (RC and

CC1) and CC2. The power ground consists of the (–)

plate of CIN, the (–) plate of COUT and Pin 4 of the

LTC3404. The power ground traces should be kept

short, direct and wide. The signal ground and power

ground should converge to a common node in a star-

ground configuration.

2. Does the VFB pin connect directly to the feedback

resistors? The resistive divider R1/R2 must be con-

nected between the (+) plate of COUT and signal ground.

3. Does the (+) plate of CIN connect to VIN as closely as

possible? This capacitor provides the AC current to the

internal power MOSFETs.

4. Keep the switching node SW away from sensitive small

signal nodes.

Design Example

As a design example, assume the LTC3404 is used in a

single lithium-ion battery-powered cellular phone applica-

tion. The input voltage will be operating from a maximum

of 4.2V down to about 2.7V. The load current requirement

is a maximum of 0.3A but most of the time it will be in

standby mode, requiring only 2mA. Efficiency at both low

and high load currents is important. Output voltage is

2.5V. With this information we can calculate L using

equation (1),

OUT

= () Δ()

−

⎛

⎝⎜

⎞

⎠⎟

(3)

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