11

LTC3404

3404fb

APPLICATIO S I FOR ATIO

Figure 5. Phase-Locked Loop Block Diagram

SYNC/

MODE

PHASE

DETECTOR

DIGITAL

PHASE/

FREQUENCY

DETECTOR

2.4V

VCO

3404 F05

PLL LPF

Figure 4. Relationship Between Oscillator

Frequency and Voltage at PLL LPF Pin

0.4

1.6

3404 • F04

0.8

1.2

2.0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.6

1.0

1.4

1.8

Phase-Locked Loop and Frequency Synchronization

The LTC3404 has an internal voltage-controlled oscillator

and phase detector comprising a phase-locked loop. This

allows the top MOSFET turn-on to be locked to the rising

edge of an external frequency source. The frequency range

of the voltage-controlled oscillator is 1MHz to 1.7MHz. The

phase detector used is an edge sensitive digital type that

provides zero degrees phase shift between the

external and internal oscillators. This type of phase detec-

tor will not lock up on input frequencies close to the har-

–400kHz.

The output of the phase detector is a pair of complemen-

tary current sources charging or discharging the external

filter network on the PLL LPF pin. The relationship

between the voltage on the PLL LPF pin and operating

frequency is shown in Figure 4. A simplified block diagram

is shown in Figure 5.

1.4MHz, the center frequency, current is sourced

continuously, pulling up the PLL LPF pin. When the

external frequency is less than 1.4MHz, current is sunk

continuously, pulling down the PLL LPF pin. If the

external and internal frequencies are the same but exhibit

a phase difference, the current sources turn on for an

amount of time corresponding to the phase difference.

Thus the voltage on the PLL LPF pin is adjusted until the

phase and frequency of the external and internal oscilla-

tors are identical. At this stable operating point the phase

comparator output is high impedance and the filter

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

0.01

μF. When not synchronized to an external clock, the

internal connection to the VCO is disconnected. This

disallows setting the internal oscillator frequency by a DC

Efficiency Considerations

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%. It is

often useful to analyze individual losses to determine what

is limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as:

Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage

of input power.

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

loss dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve at