LTC3404MPMS8 datasheet(12/16 Pages) LINER

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LTC3404

3404fb

LOAD CURRENT (mA)

0.1

0.00001

0.001

100

1000

3404 F06

0.0001

0.01

0.1

VOUT = 1.5V

VOUT = 2.5V

VOUT = 3.3V

VIN = 4.2V

L = 4.7

μH

Burst Mode OPERATION

Figure 6. Power Lost vs Load Current

APPLICATIO S I FOR ATIO

very low load currents can be misleading since the actual

power lost is of no consequence as illustrated in Figure 6.

1. The VIN quiescent current is due to two components:

the DC bias current as given in the electrical character-

istics and the internal main switch and synchronous

switch gate charge currents. The gate charge current

results from switching the gate capacitance of the

internal power MOSFET switches. Each time the gate is

switched from high to low to high again, a packet of

charge dQ moves from VIN to ground. The resulting

dQ/dt is the current out of VINthat is typically larger than

the DC bias current. In continuous mode, IGATECHG =

f(QT + QB) where QT and QB are the gate charges of the

internal top and bottom switches. Both the DC bias and

gate charge losses are proportional to VIN and thus

their effects will be more pronounced at higher supply

voltages.

2. I2R losses are calculated from the resistances of the

internal switches, RSW, and external inductor RL. In

continuous mode the average output current flowing

through inductor L is “chopped” between the main

switch and the synchronous switch. Thus, the series

resistance looking into the SW pin is a function of both

top and bottom MOSFET RDS(ON) and the duty cycle

(DC) as follows:

RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs can

be obtained from the Typical Performance Charateristics

curves. Thus, to obtain I2R losses, simply add RSW to

RL and multiply the result by the square of the average

output current.

Other losses including CIN and COUT ESR dissipative

losses and inductor core losses generally account for less

than 2% total additional loss.

Thermal Considerations

In most applications the LTC3404 does not dissipate

much heat due to its high efficiency. But, in applications

where the LTC3404 is running at high ambient tempera-

ture with low supply voltage and high duty cycles, such

as in dropout, the heat dissipated may exceed the maxi-

mum junction temperature of the part. If the junction

temperature reaches approximately 175

°C, both power

switches will be turned off and the SW node will become

high impedance.

To avoid the LTC3404 from exceeding the maximum

junction temperature, the user will need to do some

thermal analysis. The goal of the thermal analysis is to

determine whether the power dissipated exceeds the

maximum junction temperature of the part. The tempera-

ture rise is given by:

TR = (PD)(θJA)

where PD is the power dissipated by the regulator and qJA

is the thermal resistance from the junction of the die to the

ambient temperature.

The junction temperature, TJ, is given by:

TJ = TA + TR

where TA is the ambient temperature.

As an example, consider the LTC3404 in dropout at an

input voltage of 3V, a load current of 500mA, and an

ambient temperature of 70

°C. From the typical perfor-

mance graph of switch resistance, the RDS(ON) of the

P-channel switch at 70

°C is approximately 0.7Ω. There-

fore, power dissipated by the part is:

PD = ILOAD2 • RDS(ON) = 0.175W

For the MSOP package, the

θJA is 150°C/W. Thus, the

junction temperature of the regulator is:

TJ = 70°C + (0.175)(150) = 96°C

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