поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

AD9974BBCZ датащи(PDF) 45 Page - Analog Devices

номер детали AD9974BBCZ
подробное описание детали  Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing Core
PDF  52 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9974BBCZ датащи(HTML) 45 Page - Analog Devices

Back Button AD9974BBCZ Datasheet HTML 41Page - Analog Devices AD9974BBCZ Datasheet HTML 42Page - Analog Devices AD9974BBCZ Datasheet HTML 43Page - Analog Devices AD9974BBCZ Datasheet HTML 44Page - Analog Devices AD9974BBCZ Datasheet HTML 45Page - Analog Devices AD9974BBCZ Datasheet HTML 46Page - Analog Devices AD9974BBCZ Datasheet HTML 47Page - Analog Devices AD9974BBCZ Datasheet HTML 48Page - Analog Devices AD9974BBCZ Datasheet HTML 49Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 45 / 52 page
background image
AD9974
Rev. A | Page 45 of 52
Table 27. Timing Core Registers
Address
Data Bit
Content
Default
Value
Update
Name
Description
0x30
[5:0]
0
SCK
H1POSLOC
H1 Rising Edge Location.
[7:6]
Unused
Set unused bits to 0.
[13:8]
20
H1NEGLOC
H1 Falling Edge Location.
[15:14]
0
TESTMODE
Test Operation Only. Set to 0.
[16]
1
H1POL
H1 Polarity Control.
0 = inverse of Figure 21.
1 = no inversion.
[27:17]
Unused
Set unused bits to 0.
0x31
[5:0]
0
SCK
H2POSLOC
H2 Rising Edge Location.
[7:6]
Unused
Set unused bits to 0.
[13:8]
20
H2NEGLOC
H2 Falling Edge Location.
[15:14]
0
TESTMODE
Test Operation Only. Set to 0.
[16]
1
H2POL
H2 Polarity Control.
0 = inverse of Figure 21.
1 = no inversion.
[27:17]
Unused
Set unused bits to 0.
0x32
[5:0]
0
SCK
TESTMODE
Test Operation Only. Set to 0.
[7:6]
Unused
Set unused bits to 0.
[13:8]
20
TESTMODE
Test Operation Only. Set to 20.
[15:14]
0
TESTMODE
Test Operation Only. Set to 0.
[16]
1
TESTMODE
Test Operation Only. Set to 1.
[27:17]
Unused
Set unused bits to 0.
0x33
[5:0]
0
SCK
RGPOSLOC
RG Rising Edge Location.
[7:6]
Unused
Set unused bits to 0.
[13:8]
10
RGNEGLOC
RG Falling Edge Location.
[15:14]
0
TESTMODE
Test Operation Only. Set to 0.
[16]
1
RGPOL
RG Polarity Control.
0 = inverse of Figure 21.
1 = no inversion.
[27:17]
Unused
Set unused bits to 0.
0x34
[0]
0
SCK
H1BLKRETIME
Retime H1 HBLK to Internal Clock.
0 = no retime.
1 = enable retime.
Recommended setting is enable retime. Enabling retime adds one
cycle delay to programmed HBLK positions.
[1]
0
H2BLKRETIME
Retime H2 HBLK to Internal Clock.
[2]
0
TESTMODE
Test Operation Only. Set to 0
[3]
0
TESTMODE
Test Operation Only. Set to 0
[7:4]
0
HCLK_WIDTH
Enables wide H-clocks during HBLK interval.
0 = disable (see Table 13).
[27:8]
Unused
Set unused bits to 0.
0x35
[2:0]
1
SCK
H1DRV
H1 Drive Strength.
0 = off.
1 = 4.3 mA.
2 = 8.6 mA.
3 = 12.9 mA.
4 = 17.2 mA.
5 = 21.5 mA.
6 = 25.8 mA.
7 = 30.1 mA.
[3]
Unused
Set unused bits to 0.
[6:4]
1
H2DRV
H2 Drive Strength.
[7]
Unused
Set unused bits to 0.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com