AD9974BBCZ datasheet(32/52 Pages) AD

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AD9974

Rev. A | Page 32 of 52

Variable Gain Amplifier

Optical Black Clamp

The VGA stage provides a gain range of approximately 6 dB to

42 dB, programmable with 10-bit resolution through the serial

digital interface. A gain of 6 dB is needed to match a 1 V input

signal with the ADC full-scale range of 2 V. When compared to

1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB.

The optical black clamp loop is used to remove residual offsets

in the signal chain and track low frequency variations in the

CCD black level. During the optical black (shielded) pixel interval

on each line, the ADC output is compared with a fixed black

level reference, selected by the user in the clamp level register.

The value can be programmed between 0 LSB and 1023 LSB in

1023 steps.

The VGA gain curve follows a linear-in-dB characteristic. The

exact VGA gain is calculated for any gain register value by

The resulting error signal is filtered to reduce noise, and the

correction value is applied to the ADC input through a DAC.

Normally, the optical black clamp loop is turned on once per

horizontal line, but this loop can be updated more slowly to suit

a particular application. If external digital clamping is used during

postprocessing, the AD9974 optical black clamping can be disabled

using Bit 3 in AFE Register Address 0x00. When the loop is

disabled, the clamp level register can still be used to provide

fixed offset adjustment.

Gain (dB) = (0.0359 × Code) + 5.1 dB

where Code is the range of 0 to 1023.

VGA GAIN REGISTER CODE

127

255

383

511

639

767

895

1023

Note that if the CLPOB loop is disabled, higher VGA gain

settings reduce the dynamic range because the uncorrected

offset in the signal path is gained up.

The CLPOB pulse should be aligned with the optical black

pixels of the CCD. It is recommended that the CLPOB pulse

duration be at least 20 pixels wide. Shorter pulse widths can be

used, but the ability of the loop to track low frequency variations

in the black level is reduced. See the Horizontal Clamping and

Blanking section for more timing information.

Figure 47. VGA Gain Curve

ADC

Digital Data Outputs

The AD9974 uses a high performance ADC architecture opti-

mized for high speed and low power. Differential nonlinearity

(DNL) performance is typically better than 0.5 LSB. The ADC

uses a 2 V input range. See Figure 5, Figure 6, and Figure 7 for

typical noise performance and linearity plots for the AD9974.

The AD9974 digital output data is latched using the DOUTPHASE

in Figure 22. The switching of the data outputs can couple noise

back into the analog signal path. To minimize any switching

noise while using default SHPLOC and SHDLOC, it is

recommended that the DOUTPHASEP register be set to a value

between 36 and 47. Other settings can produce good results, but

experimentation is necessary.

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