AD9974BBCZ datasheet(31/52 Pages) AD

31 / 52 page

AD9974

Rev. A | Page 31 of 52

SHA Mode—Differential Input Configuration

This configuration uses a differential input sample/hold

amplifier (SHA) (see Figure 43).

IMAGE

SENSOR

SHA/

CDS

CCDINM

CCDINP

AD9974

Figure 43. SHA Mode—Differential Input Configuration

In this configuration, a signal is applied to the CCDINP input

and, simultaneously, an inverse signal is applied to the CCDINM

input. Sampling occurs on both signals at the same time. This

creates the differential output for amplification and the ADC

(see Figure 44 and Table 18).

(N + 1) SIGNAL SAMPLE

(N) SIGNAL SAMPLE

INPUT_POS

INPUT_NEG

PEAK SIGNAL

LEVEL (VFS)

BLACK SIGNAL LEVEL (VBLK)

MINIMUM SIGNAL LEVEL (VMIN)

GND

Figure 44. SHA Mode—Differential Input Signal

Table 18. SHA Mode—Differential Voltage Levels

Signal Level

Symbol

Min (mV)

Typ (mV)

Max (mV)

Black

VBLK

Saturation

VFS

1000

VDD − 300

1400

Minimum

VMIN

1800

SHA Mode—DC-Coupled, Single–Ended Input

The SHA mode can also be used in a single-ended fashion, with

the signal from the image sensor applied to the CDS/SHA using

a single input, CCDINP. This is similar to the differential configu-

ration, except in this case, the CCDINM line is held at a constant

dc voltage, establishing a reference level that matches the image

sensor reference voltage (see Figure 45).

IMAGE

SENSOR

SHA/

CDS

CCDINM

CCDINP

AD9974

NOTES

1. DC VOLTAGE ABOVE GROUND MAYBE USED TO

MATCH THE SENSOR REFERENCE LEVEL.

Figure 45. SHA Mode—Single–Ended Input Configuration, DC-Coupled

Referring to Figure 46 and Table 19, the CCDINM signal is a

constant dc voltage set at a level above ground potential. The

sensor signal is applied to the other input, and samples are taken

at the signal minimum and at a point of signal maximum. The

resulting differential signal is the difference between the signal

and the reference voltage.

(N + 1) SIGNAL SAMPLE

(N) SIGNAL SAMPLE

INPUT_POS

INPUT_NEG

PEAK SIGNAL

LEVEL (VFS)

BLACK SIGNAL LEVEL (VBLK)

MINIMUM SIGNAL LEVEL (VMIN)

GND

Figure 46. SHA Mode—Single–Ended Input Signal (DC-Coupled)

Table 19. SHA Mode—Single-Ended Input Voltages

Signal Level

Symbol

Min (mV)

Typ (mV)

Max (mV)

Black

VBLK

Saturation

VFS

1000

1400

Minimum

VMIN

CDS Timing Control

The timing shown in Figure 21 illustrates how the two internally

generated CDS clocks, SHP and SHD, are used to sample the

reference level and data level of the CCD signal, respectively. The

placement of the SHP and SHD sampling edges is determined by

the setting of the SHPLOC and SHDLOC register located at

Address 0x36. Placement of these two clock signals is critical in

achieving the best performance from the CCD.

SHA Timing Control

When SHA mode is selected, only the SHPLOC setting is used

to sample the input signal, but the SHDLOC signal should still

be programmed to an edge setting of SHPLOC + 32.

AD9974BBCZ датащи(PDF) 31 Page - Analog Devices

AD9974BBCZ датащи(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

датащи скачать

ссылки URL