AD9974BBCZ datasheet(33/52 Pages) AD

33 / 52 page

AD9974

Rev. A | Page 33 of 52

APPLICATIONS INFORMATION

RECOMMENDED POWER-UP SEQUENCE

When the AD9974 is powered up, the following sequence is

recommended (see Figure 48 for each step).

Turn on the power supplies for the AD9974 and apply CLI

clock. There is no required sequence for turning on each

supply.

Although the AD9974 contains an on-chip power-on reset,

a software reset of the internal registers is recommended.

Write 1 to the SW_RST register (Address 0x10) to reset all

the internal registers to their default values. This bit is self-

clearing and automatically resets to 0.

Write to the desired registers to configure high speed timing

and horizontal timing. Note that all TESTMODE registers

must be written as described in the Complete Register

Listing section.

To place the part into normal power operation, write 0 to the

STANDBY and REFBUF_PWRDN registers (Address 0x00).

The Precision Timing core must be reset by writing 1 to the

TGCORE_RST register (Address 0x14). This starts the

internal timing core operation.

Write 1 to the OUT_CONTROL register (Address 0x11).

The next VD/HD falling edge allows register updates to occur,

including OUT_CONTROL, which enables all clock outputs.

Additional Restrictions

When operating, note the following restrictions:

•

The HD falling edge should be located in the same CLI

clock cycle as the VD falling edge or after the VD falling

edge. The HD falling edge should not be located between

one and five cycles prior to the VD falling edge.

•

If possible, perform all start-up serial writes with VD and

HD disabled. This prevents unknown behavior caused by

partial updating of registers before all information is loaded.

The internal horizontal counter is reset 12 CLI cycles after the

falling edge of HD. See Figure 49 for details on how the internal

counter is reset.

POWER

SUPPLIES

CLI

(INPUT)

SERIAL

WRITES

(INPUT)

HI-Z BY

DEFAULT

CLOCKS ACTIVE WHEN OUTCONTROL

1ST FIELD

AD9974 SUPPLIES

H-CLOCKS

H1, H3, RG

H2, H4

Figure 48. Recommended Power-Up Sequence

AD9974BBCZ датащи(PDF) 33 Page - Analog Devices

AD9974BBCZ датащи(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

датащи скачать

ссылки URL