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STM32L151RDT6 датащи(PDF) 92 Page - STMicroelectronics

номер детали STM32L151RDT6
подробное описание детали  Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 384KB Flash, 48KB SRAM, 12KB EEPROM, LCD, USB, ADC, DAC, memory I/F
PDF  140 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32L151RDT6 датащи(HTML) 92 Page - STMicroelectronics

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Electrical characteristics
STM32L151xD STM32L152xD
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Doc ID 022027 Rev 6
Figure 23.
Synchronous non-multiplexed NOR/PSRAM read timings
Table 43.
Synchronous non-multiplexed NOR/PSRAM read timings(1)
1.
CL = 30 pF.
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
2*THCLK -
0.5
-
ns
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
0
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
0
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
3
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
3.5
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
0
-
ns
td(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low
-
THCLK + 1
ns
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
2.5
-
ns
tsu(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK high
4
-
ns
th(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high
4
-
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
TBD
-
ns
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
TBD
-
ns
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NOE
FSMC_D[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-AV)
td(CLKL-AIV)
td(CLKL-NOEL)
td(CLKL-NOEH)
tsu(DV-CLKH)
th(CLKH-DV)
tsu(DV-CLKH)
th(CLKH-DV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
t h(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
ai14894f
FSMC_NADV
td(CLKL-NADVL)
td(CLKL-NADVH)



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