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PIC18F1220E/SOSQTP датащи(PDF) 82 Page - Microchip Technology

номер детали PIC18F1220E/SOSQTP
подробное описание детали  18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers
PDF  308 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
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PIC18F1220E/SOSQTP датащи(HTML) 82 Page - Microchip Technology

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PIC18F1220/1320
DS39605F-page 80
© 2007 Microchip Technology Inc.
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt
Enable
registers
(PIE1,
PIE2).
When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-6:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
ADIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIE: A/D Converter Interrupt Enable bit
1
= Enables the A/D interrupt
0
= Disables the A/D interrupt
bit 5
RCIE: EUSART Receive Interrupt Enable bit
1
= Enables the EUSART receive interrupt
0
= Disables the EUSART receive interrupt
bit 4
TXIE: EUSART Transmit Interrupt Enable bit
1
= Enables the EUSART transmit interrupt
0
= Disables the EUSART transmit interrupt
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1
= Enables the CCP1 interrupt
0
= Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1
= Enables the TMR2 to PR2 match interrupt
0
= Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1
= Enables the TMR1 overflow interrupt
0
= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown



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