PIC18F1220ESLASHSOSQTP datasheet(23/308 Pages) MICROCHIP

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DS39605F-page 21

PIC18F1220/1320

3.2

Sleep Mode

The power managed Sleep mode in the PIC18F1220/

1320 devices is identical to that offered in all other PIC

microcontrollers. It is entered by clearing the IDLEN

and SCS1:SCS0 bits (this is the Reset state) and

executing the SLEEP instruction. This shuts down the

primary oscillator and the OSTS bit is cleared (see

Figure 3-1).

When a wake event occurs in Sleep mode (by interrupt,

Reset or WDT time-out), the system will not be clocked

until the primary clock source becomes ready (see

Figure 3-2), or it will be clocked from the internal

oscillator block if either the Two-Speed Start-up or the

Fail-Safe Clock Monitor are enabled (see Section 19.0

“Special Features of the CPU”). In either case, the

OSTS bit is set when the primary clock is providing the

system clocks. The IDLEN and SCS bits are not

affected by the wake-up.

3.3

Idle Modes

The IDLEN bit allows the microcontroller’s CPU to be

selectively shut down while the peripherals continue to

operate. Clearing IDLEN allows the CPU to be clocked.

Setting IDLEN disables clocks to the CPU, effectively

stopping program execution (see Register 2-2). The

peripherals continue to be clocked regardless of the

setting of the IDLEN bit.

There is one exception to how the IDLEN bit functions.

When all the low-power OSCCON bits are cleared

(IDLEN:SCS1:SCS0 = 000), the device enters Sleep

mode upon the execution of the SLEEP instruction. This

is both the Reset state of the OSCCON register and the

setting that selects Sleep mode. This maintains

compatibility with other PIC devices that do not offer

power managed modes.

If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a

‘1’ when a SLEEP instruction is executed, the

peripherals will be clocked from the clock source

selected using the SCS1:SCS0 bits; however, the CPU

will not be clocked. Since the CPU is not executing

instructions, the only exits from any of the Idle modes

are by interrupt, WDT time-out or a Reset.

When a wake event occurs, CPU execution is delayed

approximately 10

μs while it becomes ready to execute

code. When the CPU begins executing code, it is

clocked by the same clock source as was selected in

the power managed mode (i.e., when waking from

RC_IDLE mode, the internal oscillator block will clock

the CPU and peripherals until the primary clock source

becomes ready – this is essentially RC_RUN mode).

This continues until the primary clock source becomes

ready. When the primary clock becomes ready, the

OSTS bit is set and the system clock source is

switched to the primary clock (see Figure 3-4). The

IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT

time-out will result in a WDT wake-up to full power

operation.

TABLE 3-2:

COMPARISON BETWEEN POWER MANAGED MODES

Power

Managed

Mode

CPU is Clocked by ...

WDT Time-out

causes a ...

Peripherals are

Clocked by ...

Clock during Wake-up

(while primary becomes

ready)

Sleep

Not clocked (not running) Wake-up

Not clocked

None or INTOSC multiplexer

if Two-Speed Start-up or

Fail-Safe Clock Monitor are

enabled

Any Idle mode

Not clocked (not running) Wake-up

Primary, Secondary or

INTOSC multiplexer

Unchanged from Idle mode

(CPU operates as in

corresponding Run mode)

Any Run mode

Primary or secondary

clocks or INTOSC

multiplexer

Reset

Primary or secondary

clocks or INTOSC

multiplexer

Unchanged from Run mode

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