PIC18F1220ESLASHSOSQTP datasheet(46/308 Pages) MICROCHIP

46 / 308 page

PIC18F1220/1320

DS39605F-page 44

5.3

Fast Register Stack

A “fast return” option is available for interrupts. A fast

BSR registers and is only one in depth. The stack is not

readable or writable and is loaded with the current

value of the corresponding register when the processor

vectors for an interrupt. The values in the registers are

then loaded back into the working registers, if the

RETFIE, FAST

instruction is used to return from the

interrupt.

All interrupt sources will push values into the stack

registers. If both low and high priority interrupts are

enabled, the stack registers cannot be used reliably to

return from low priority interrupts. If a high priority inter-

rupt occurs while servicing a low priority interrupt, the

stack register values stored by the low priority interrupt

will be overwritten. Users must save the key registers

in software during a low priority interrupt.

If interrupt priority is not used, all interrupts may use the

fast register stack for returns from interrupt.

If no interrupts are used, the fast register stack can be

used to restore the Status, WREG and BSR registers at

the end of a subroutine call. To use the fast register

stack for a subroutine call, a CALL LABEL, FAST

instruction must be executed to save the Status,

WREG and BSR registers to the fast register stack. A

RETURN, FAST

instruction is then executed to restore

these registers from the fast register stack.

Example 5-1 shows a source code example that uses

the fast register stack during a subroutine call and

return.

EXAMPLE 5-1:

FAST REGISTER STACK

CODE EXAMPLE

5.4

PCL, PCLATH and PCLATU

The Program Counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21-bits

wide. The low byte, known as the PCL register, is both

readable and writable. The high byte, or PCH register,

contains the PC<15:8> bits and is not directly readable

or writable. Updates to the PCH register may be per-

formed through the PCLATH register. The upper byte is

called PCU. This register contains the PC<20:16> bits

and is not directly readable or writable. Updates to the

PCU register may be performed through the PCLATU

The contents of PCLATH and PCLATU will be

transferred to the program counter by any operation

that writes PCL. Similarly, the upper two bytes of the

program counter will be transferred to PCLATH and

PCLATU by an operation that reads PCL. This is useful

for computed offsets to the PC (see Section 5.8.1

“Computed GOTO”).

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the LSB of PCL is fixed to a value of ‘0’.

The PC increments by 2 to address sequential

instructions in the program memory.

The CALL, RCALL, GOTO and program branch instruc-

tions write to the program counter directly. For these

instructions, the contents of PCLATH and PCLATU are

not transferred to the program counter.

CALL SUB1, FAST

;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

•

SUB1

•

RETURN, FAST

;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

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