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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSPIC33FJMC202ESS датащи(PDF) 177 Page - Microchip Technology |
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DSPIC33FJMC202ESS датащи(HTML) 177 Page - Microchip Technology |
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177 / 330 page  © 2007-2012 Microchip Technology Inc. DS70283K-page 177 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 16-2: DFLTxCON: DIGITAL FILTER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — —IMV<1:0> CEID bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 QEOUT QECK<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 IMV<1:0>: Index Match Value bits – These bits allow the user application to specify the state of the QEA and QEB input pins during an Index pulse when the POSxCNT register is to be reset. In 4X Quadrature Count Mode: IMV1 = Required State of Phase B input signal for match on index pulse IMV0 = Required State of Phase A input signal for match on index pulse In 2X Quadrature Count Mode: IMV1 = Selects Phase input signal for Index state match (0 = Phase A, 1 = Phase B) IMV0 = Required state of the selected Phase input signal for match on index pulse bit 8 CEID: Count Error Interrupt Disable bit 1 = Interrupts due to count errors are disabled 0 = Interrupts due to count errors are enabled bit 7 QEOUT: QEA/QEB/INDX Pin Digital Filter Output Enable bit 1 = Digital filter outputs enabled 0 = Digital filter outputs disabled (normal pin operation) bit 6-4 QECK<2:0>: QEA/QEB/INDX Digital Filter Clock Divide Select Bits 111 = 1:256 Clock Divide 110 = 1:128 Clock Divide 101 = 1:64 Clock Divide 100 = 1:32 Clock Divide 011 = 1:16 Clock Divide 010 = 1:4 Clock Divide 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide bit 3-0 Unimplemented: Read as ‘0’ |
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