DSPIC33FJMC202ESS datasheet(68/330 Pages) MICROCHIP

68 / 330 page

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

DS70283K-page 68

FIGURE 6-3:

BROWN-OUT SITUATIONS

6.5

External Reset (EXTR)

The external Reset is generated by driving the MCLR

pin low. The MCLR pin is a Schmitt trigger input with an

additional glitch filter. Reset pulses that are longer than

the minimum pulse-width will generate a Reset. Refer

to Section 24.0 “Electrical Characteristics” for

minimum pulse-width specifications. The External

Reset (MCLR) Pin (EXTR) bit in the Reset Control

6.5.1

EXTERNAL SUPERVISORY CIRCUIT

Many systems have external supervisory circuits that

generate reset signals to Reset multiple devices in the

system. This external Reset signal can be directly

connected to the MCLR pin to Reset the device when

the rest of system is Reset.

6.5.2

INTERNAL SUPERVISORY CIRCUIT

When using the internal power supervisory circuit to

Reset the device, the external reset pin (MCLR) should

be tied directly or resistively to VDD. In this case, the

MCLR pin will not be used to generate a Reset. The

external reset pin (MCLR) does not have an internal

pull-up and must not be left unconnected.

6.6

Software RESET Instruction (SWR)

Whenever the RESET instruction is executed, the

device will assert SYSRST, placing the device in a

special Reset state. This Reset state will not

re-initialize the clock. The clock source in effect prior to

the RESET instruction will remain. SYSRST is released

at the next instruction cycle, and the reset vector fetch

will commence.

The Software Reset (Instruction) Flag (SWR) bit in the

Reset Control register (RCON<6>) is set to indicate

the software Reset.

6.7

Watchdog Time-out Reset (WDTO)

Whenever a Watchdog time-out occurs, the device will

asynchronously assert SYSRST. The clock source will

remain unchanged. A WDT time-out during Sleep or

Idle mode will wake-up the processor, but will not reset

the processor.

The Watchdog Timer Time-out Flag bit (WDTO) in the

Reset Control register (RCON<4>) is set to indicate

the

Watchdog

Reset.

Refer

Section 21.4

“Watchdog Timer (WDT)” for more information on

Watchdog Reset.

6.8

Trap Conflict Reset

If a lower-priority hard trap occurs while a

higher-priority trap is being processed, a hard trap

conflict Reset occurs. The hard traps include

exceptions of priority level 13 through level 15,

inclusive. The address error (level 13) and oscillator

error (level 14) traps fall into this category.

The Trap Reset Flag bit (TRAPR) in the Reset Control

Reset. Refer to Section 7.0 “Interrupt Controller” for

more information on trap conflict Resets.

VDD

SYSRST

VBOR

VDD

SYSRST

VBOR

VDD

SYSRST

VBOR

TBOR + TPWRT

VDD dips before PWRT expires

TBOR + TPWRT

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