DSPIC33FJMC202ESS datasheet(76/330 Pages) MICROCHIP

76 / 330 page

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

DS70283K-page 76

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

NSTDIS

OVAERR

OVBERR

COVAERR

COVBERR

OVATE

OVBTE

COVTE

bit 15

bit 8

R/W-0

U-0

R/W-0

U-0

SFTACERR

DIV0ERR

—

MATHERR

ADDRERR

STKERR

OSCFAIL

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled

0 = Interrupt nesting is enabled

bit 14

OVAERR: Accumulator A Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator A

0 = Trap was not caused by overflow of Accumulator A

bit 13

OVBERR: Accumulator B Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator B

0 = Trap was not caused by overflow of Accumulator B

bit 12

COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit

1 = Trap was caused by catastrophic overflow of Accumulator A

0 = Trap was not caused by catastrophic overflow of Accumulator A

bit 11

COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit

1 = Trap was caused by catastrophic overflow of Accumulator B

0 = Trap was not caused by catastrophic overflow of Accumulator B

bit 10

OVATE: Accumulator A Overflow Trap Enable bit

1 = Trap overflow of Accumulator A

0 = Trap disabled

bit 9

OVBTE: Accumulator B Overflow Trap Enable bit

1 = Trap overflow of Accumulator B

0 = Trap disabled

bit 8

COVTE: Catastrophic Overflow Trap Enable bit

1 = Trap on catastrophic overflow of Accumulator A or B enabled

0 = Trap disabled

bit 7

SFTACERR: Shift Accumulator Error Status bit

1 = Math error trap was caused by an invalid accumulator shift

0 = Math error trap was not caused by an invalid accumulator shift

bit 6

DIV0ERR: Arithmetic Error Status bit

1 = Math error trap was caused by a divide by zero

0 = Math error trap was not caused by a divide by zero

bit 5

Unimplemented: Read as ‘0’

bit 4

MATHERR: Arithmetic Error Status bit

1 = Math error trap has occurred

0 = Math error trap has not occurred

bit 3

ADDRERR: Address Error Trap Status bit

1 = Address error trap has occurred

0 = Address error trap has not occurred

DSPIC33FJMC202ESS датащи(PDF) 76 Page - Microchip Technology

DSPIC33FJMC202ESS датащи(HTML) 76 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL