ADXL375 datasheet(24/32 Pages) AD

24 / 32 page

ADXL375

Data Sheet

Rev. 0 | Page 24 of 32

SELF_TEST SPI

INT_INVERT 0

Justify

The DATA_FORMAT register controls the presentation of data

to Register 0x32 through Register 0x37.

SELF_TEST Bit

A setting of 1 in the SELF_TEST bit applies a self-test force to the

sensor, causing a shift in the output data. A value of 0 disables the

self-test force. For more information about the self-test function,

see the Self-Test section and the Using Self-Test section.

SPI Bit

A value of 1 in the SPI bit configures the device for 3-wire SPI

mode; a value of 0 configures the device for 4-wire SPI mode.

INT_INVERT Bit

A value of 0 in the INT_INVERT bit sets the polarity of the

interrupt pins to active high; a value of 1 sets the polarity of

the interrupt pins to active low.

Justify Bit

A setting of 1 in the justify bit selects left justified (MSB) mode; a

setting of 0 selects right justified (LSB) mode with sign extension.

DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)

These six bytes (Register 0x32 to Register 0x37) are each eight

bits in length and contain the output data for each axis.

•

for the x-axis.

•

for the y-axis.

•

for the z-axis.

The output data is in twos complement format. DATAx0 is

the least significant byte, and DATAx1 is the most significant

byte (x represents X, Y, or Z). The DATA_FORMAT register

(Address 0x31) controls the format of the data. It is recommended

that a multiple-byte read of all six registers be performed to

prevent a change in data between reads of sequential registers.

When using the 3200 Hz or 1600 Hz output data rate, the LSB of

the output data-word is always 0. When the data is right justified,

the LSB corresponds to Bit D0 of the DATAx0 register; when the

data is left justified, the LSB corresponds to Bit D3 of the DATAx0

FIFO_MODE

Trigger

Samples

The FIFO_CTL register is used to configure the FIFO buffer for

the device. For more information, see the FIFO Buffer section.

For an in-depth description of the FIFO buffer, see the AN-1025

Application Note, Utilization of the First In, First Out (FIFO) Buffer

in Analog Devices, Inc., Digital Accelerometers.

FIFO_MODE Bits

These bits set the FIFO mode, as described in Table 17.

Table 17. FIFO Modes

Setting

FIFO

Mode

Description

Bypass

FIFO buffer is bypassed.

FIFO

FIFO buffer collects up to 32 samples and

then stops collecting data, collecting new

data only when the buffer is not full.

Stream

FIFO buffer holds the last 32 samples.

When the buffer is full, the oldest data

is overwritten with newer data.

Trigger

FIFO buffer holds the last samples before

the trigger event and continues to collect

data until full. New data is collected only

when the buffer is not full.

Trigger Bit

A value of 0 in the trigger bit links the trigger event of trigger

mode to the INT1 pin, and a value of 1 links the trigger event

to the INT2 pin.

Samples Bits

The function of the samples bits depends on the FIFO mode

selected (see Table 18). Entering a value of 0 in the samples bits

immediately sets the watermark bit in the INT_SOURCE register,

regardless of the FIFO mode selected. Undesirable operation may

occur if a value of 0 is used for the samples bits when trigger

mode is used.

Table 18. Samples Bits Functions

FIFO Mode

Samples Bits Function

Bypass

None.

FIFO

Specifies how many FIFO entries are needed to

trigger a watermark interrupt.

Stream

Specifies how many FIFO entries are needed to

trigger a watermark interrupt.

Trigger

Specifies how many FIFO samples are retained in

the FIFO buffer before a trigger event.

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