ADXL375 datasheet(19/32 Pages) AD

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Data Sheet

ADXL375

Rev. 0 | Page 19 of 32

Table 14. I2C Timing (TA = 25°C, VS = 2.5 V, VDDI/O = 1.8 V)

Limit1, 2

Parameter

Min

Max

Unit

Description

fSCL

400

kHz

SCL clock frequency

2.5

µs

SCL cycle time

0.6

µs

SCL high time

1.3

µs

SCL low time

0.6

µs

Hold time for start/repeated start condition

100

Data setup time

t63, 4, 5

0.9

µs

Data hold time

0.6

µs

Setup time for repeated start condition

0.6

µs

Setup time for stop condition

1.3

µs

Bus-free time between a stop condition and a start condition

t10

300

Rise time of SCL and SDA when receiving

Rise time of SCL and SDA when receiving or transmitting

t11

300

Fall time of SCL and SDA when receiving

250

Fall time of SCL and SDA when transmitting

400

Capacitive load for each bus line

Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested.

The timing values are referred to the input thresholds (VIL and VIH) given in Table 13.

t6 is the data hold time that is measured from the falling edge of SCL. It applies to data during the transmission and acknowledge phases.

To bridge the undefined region of the falling edge of SCL, a transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with

respect to VIH,MIN of the SCL signal).

The maximum value for t6 must be met only if the device does not stretch the low period (t3) of the SCL signal. The maximum value for t6 is a function of the clock low

time (t3), the clock rise time (t10), and the minimum data setup time (t5(MIN)). This value is calculated as t6(MAX) = t3 − t10 − t5(MIN).

SDA

SCL

t10

t11

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

Figure 30. I2C Timing Diagram

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