ADXL375 datasheet(22/32 Pages) AD

22 / 32 page

ADXL375

Data Sheet

Rev. 0 | Page 22 of 32

ACT_x Enable and INACT_x Enable Bits

A setting of 1 for the ACT_x enable and INACT_x enable bits

enables x-, y-, or z-axis participation in detecting activity or

inactivity. A setting of 0 excludes the selected axis from participa-

tion. If all axes are excluded, the function is disabled. For activity

detection, all participating axes are logically OR’ed, causing the

activity function to be triggered when any participating axis

exceeds the activity threshold. For inactivity detection, all parti-

cipating axes are logically AND’ed, causing the inactivity function

to be triggered only if all participating axes are below the inactivity

threshold for the specified time.

Suppress SHOCK_X enable SHOCK_Y enable SHOCK_Z enable

The SHOCK_AXES register specifies the participation of each

of the three axes in single shock/double shock detection.

Suppress Bit

Setting the suppress bit suppresses double shock detection if

acceleration greater than the value in the THRESH_SHOCK

more information, see the Shock Detection section.

SHOCK_x Enable Bits

A setting of 1 in the SHOCK_X enable, SHOCK_Y enable, or

SHOCK_Z enable bit enables x-, y-, or z-axis participation in

shock detection. A setting of 0 excludes the selected axis from

participation in shock detection.

ACT_X source

ACT_Y source

ACT_Z source

Asleep

SHOCK_X source SHOCK_Y source SHOCK_Z source

The read-only ACT_SHOCK_STATUS register indicates the

first axis involved in an activity or shock event.

ACT_x Source and SHOCK_x Source Bits

The ACT_x source and SHOCK_x source bits indicate the

first axis involved in an activity or shock event. A setting of 1

corresponds to involvement in the event; a setting of 0 corre-

sponds to no involvement. When new data is available, these

bits are not cleared but are overwritten by the new data. Read

the ACT_SHOCK_STATUS register before clearing the inter-

rupt. Disabling an axis from participation in activity or shock

events clears the corresponding source bit in this register when

the next activity or single shock/double shock event occurs.

Asleep Bit

A setting of 1 in the asleep bit indicates that the part is asleep; a

setting of 0 indicates that the part is not asleep. This bit toggles

only if the device is configured for autosleep. For more informa-

tion about the autosleep mode, see the AUTO_SLEEP Bit section.

LOW_POWER

Rate

The BW_RATE register configures the device bandwidth

and output data rate; this register also enables and disables

low power mode.

LOW_POWER Bit

A setting of 0 in the LOW_POWER bit selects normal opera-

tion; a setting of 1 selects reduced power operation, which has

somewhat higher noise. For more information, see the Low

Power Mode section.

Rate Bits

The rate bits select the device bandwidth and output data rate

(see Table 6 and Table 8). The default value for these bits is 0x0A,

which translates to a 100 Hz output data rate. The selected output

data rate must be appropriate for the communication protocol

and frequency selected. Selecting an output data rate that is too

high for the communication speed may result in samples being

discarded (for more information, see the Serial Communications

section).

Link

AUTO_SLEEP Measure Sleep

Wakeup

The POWER_CTL register can be used to configure the device

for autosleep mode; this register is also used to set the device to

measurement mode or standby mode.

Link Bit

The link bit serially links the activity and inactivity functions. If

both the activity and inactivity functions are enabled, a setting of

1 in the link bit delays the start of the activity detection function

until inactivity is detected. After activity is detected, inactivity

detection begins, preventing the detection of activity. When this

bit is set to 0, the inactivity and activity functions are concurrent.

For more information about the link feature, see the Link Mode

section.

Before clearing the link bit, it is recommended that the part be

placed in standby mode (set the measure bit, Bit D3, to 0). After

clearing the link bit, reset the part to measurement mode (set the

measure bit, Bit D3, to 1). This configuration sequence ensures

that the device is properly biased if sleep mode is manually

disabled; otherwise, the first few samples of data after the link

bit is cleared may have additional noise, especially if the device

is asleep when the bit is cleared.

ADXL375 датащи(PDF) 22 Page - Analog Devices

ADXL375 датащи(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

датащи скачать

ссылки URL