ADXL375 datasheet(23/32 Pages) AD

23 / 32 page

Data Sheet

ADXL375

Rev. 0 | Page 23 of 32

AUTO_SLEEP Bit

If the link bit is set, a setting of 1 in the AUTO_SLEEP bit

enables the autosleep function. In autosleep mode, the ADXL375

automatically switches to sleep mode if the inactivity function is

enabled and inactivity is detected (that is, when acceleration is

below the THRESH_INACT value for at least the time specified

by the TIME_INACT value). If activity detection is also enabled,

the ADXL375 automatically wakes up from sleep after detecting

activity and returns to operation at the output data rate set in

the BW_RATE register. A setting of 0 in the AUTO_SLEEP bit

disables automatic switching to sleep mode.

If the link bit is not set, the AUTO_SLEEP feature is disabled and

setting the AUTO_SLEEP bit has no effect on device operation.

For more information about the link feature, see the Link Bit

section and the Link Mode section. For more information about

autosleep mode, see the Autosleep Mode section.

Before clearing the AUTO_SLEEP bit, it is recommended that the

part be placed in standby mode (set the measure bit, Bit D3, to 0).

After clearing the AUTO_SLEEP bit, reset the part to measure-

ment mode (set the measure bit, Bit D3, to 1). This configuration

sequence ensures that the device is properly biased if sleep mode

is manually disabled; otherwise, the first few samples of data after

the AUTO_SLEEP bit is cleared may have additional noise,

especially if the device is asleep when the bit is cleared.

Measure Bit

A setting of 0 in the measure bit places the part into standby

mode; a setting of 1 places the part into measurement mode.

The ADXL375 powers up in standby mode with minimum

power consumption (see the Power Sequencing section).

Sleep Bit

A setting of 0 in the sleep bit places the part into the normal

mode of operation; a setting of 1 places the part into sleep mode.

Sleep mode suppresses the DATA_READY interrupt, stops trans-

mission of data to the FIFO buffer, and switches the sampling

rate to the rate specified by the wakeup bits (Bits[D1:D0]). In

sleep mode, only the activity function can be used. When the

DATA_READY interrupt is suppressed, the output data registers

(Register 0x32 to Register 0x37) are still updated at the sampling

rate set by the wakeup bits.

Before clearing the sleep bit, it is recommended that the part be

placed in standby mode (set the measure bit, Bit D3, to 0). After

clearing the sleep bit, reset the part to measurement mode (set the

measure bit, Bit D3, to 1).

Wakeup Bits

The wakeup bits control the sampling rate during sleep mode

(see Table 16).

Table 16. Sampling Rate in Sleep Mode

Setting

Frequency (Hz)

DATA_READY

SINGLE_SHOCK

DOUBLE_SHOCK

Activity

Inactivity

Watermark

Overrun

A setting of 1 for any bit in the INT_ENABLE register enables

the specified function to generate interrupts; a setting of 0 for

any bit in this register prevents the function from generating

interrupts. The DATA_READY, watermark, and overrun bits

enable only the interrupt output; the functions are always

enabled. It is recommended that interrupts be configured in

For more information about the interrupts, see the Bits in the

Interrupt Registers section.

DATA_READY

SINGLE_SHOCK

DOUBLE_SHOCK

Activity

Inactivity

Watermark

Overrun

A setting of 0 for any bit in the INT_MAP register causes the

specified interrupt to be sent to the INT1 pin; a setting of 1 for

any bit in this register causes the specified interrupt to be sent to

the INT2 pin. All selected interrupts for a given pin are OR’ed.

DATA_READY

SINGLE_SHOCK

DOUBLE_SHOCK

Activity

Inactivity

Watermark

Overrun

X = ignore this bit.

A setting of 1 for any bit in the INT_SOURCE register indicates

that the specified function has triggered an interrupt; a setting of

0 for any bit in this register indicates that the specified function

has not triggered an interrupt. The DATA_READY, watermark,

and overrun bits are always set if the corresponding interrupt

occurs, regardless of the settings in the INT_ENABLE register;

these bits are cleared by reading data from the data registers

(Address 0x32 to Address 0x37). The DATA_READY and water-

mark bits may require multiple reads to be cleared. Other bits,

and their corresponding interrupts, are cleared by reading the

INT_SOURCE register.

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