MPC8315CVRADDA datasheet(19/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

DDR and DDR2 SDRAM

This table provides the DDR2 capacitance when GVDD(typ) = 1.8 V.

This table provides the recommended operating conditions for the DDR SDRAM component(s) of the

MPC8315E when GVDD(typ) = 2.5 V.

This table provides the DDR capacitance when GVDD(typ) = 2.5 V.

Note:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5

 GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V

 V

OUT GVDD.

Table 12. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input/output capacitance: DQ, DQS

CIO

Delta input/output capacitance: DQ, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

Table 13. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V

Parameter/Condition

Symbol

Min

Max

Unit

Note

I/O supply voltage

GVDD

2.3

2.7

I/O reference voltage

MVREF

0.49

 GVDD

0.51

 GVDD

I/O termination voltage

VTT

MVREF – 0.04

MVREF + 0.04

Input high voltage

VIH

MVREF + 0.15

GVDD + 0.3

—

Input low voltage

VIL

–0.3

MVREF – 0.15

—

Output leakage current

IOZ

–9.9

A4

Output high current (VOUT = 1.95 V,

GVDD = 2.3V)

IOH

–16.2

—

Output low current (VOUT = 0.35 V)

IOL

16.2

—

Note:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5

 GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V

 V

OUT GVDD.

Table 14. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V Interface

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input/output capacitance: DQ,DQS

CIO

Table 11. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)

Parameter/Condition

Symbol

Min

Max

Unit

Note

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