MPC8315CVRADDA datasheet(93/106 Pages) FREESCALE

93 / 106 page

MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Clocking

As described in Section 24, “Clocking,” The LBCM, DDRCM, and SPMF parameters in the reset

configuration word low and the CFG_SYS_CLKIN_DIV configuration input signal select the ratio

between the primary clock input (SYS_CLK_IN or PCI_CLK) and the internal coherent system bus clock

(csb_clk). Table 74 and Table 75 shows the expected frequency values for the CSB frequency for select

csb_clk to SYS_CLK_IN/PCI_SYNC_IN ratios.

Table 73. System PLL Multiplication Factors

RCWL[SPMF]

System PLL

Multiplication Factor

0000

Reserved

0001

Reserved

0010

 2

0011

 3

0100

 4

0101

 5

0110–1111

Reserved

Table 74. CSB Frequency Options for Host Mode

CFG_SYS_CLKIN_DIV

at Reset1

1 CFG_SYS_CLKIN_DIV select the ratio between SYS_CLK_IN and PCI_SYNC_OUT.

SPMF

csb_clk :

Input Clock

Ratio 2

2 SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

Input Clock

Frequency (MHz)2

33.33

66.67

High/Low 3

3 In the Host mode it does not matter if the value is High or Low.

0010

2:1

133

High/Low

0011

3:1

100

—

High/Low

0100

4:1

133

—

High/Low

0101

5:1

120

—

Table 75. CSB Frequency Options for Agent Mode

CFG_SYS_CLKIN_DIV

at Reset1

1 CFG_SYS_CLKIN_DIV doubles csb_clk if set low.

SPMF

csb_clk :

Input Clock

Ratio 2

2 SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

Input Clock

frequency (MHz)2

33.33

66.67

High

0010

2: 1

133

High

0011

3: 1

100

—

High

0100

4: 1

133

—

High

0101

5: 1

120

—

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