MPC8315CVRADDA datasheet(47/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

I2C

This figure provides the test access port timing diagram.

Figure 32. Test Access Port Timing Diagram

13 I2C

This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8315E.

13.1

I2C DC Electrical Characteristics

This table provides the DC electrical characteristics for the I2C interface.

Table 47. I2C DC Electrical Characteristics

At recommended operating conditions with NVDD of 3.3 V ± 300 mv

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage level

VIH

0.7

 NVDD

NVDD + 0.3

—

Input low voltage level

VIL

–0.3

0.3

 NVDD

—

Low level output voltage

VOL

00.2

 NVDD

High level output voltage

VOH

0.8

 NVDD

NVDD + 0.3

—

Output fall time from VIH(min) to VIL(max) with a bus

capacitance from 10 to 400 pF

tI2KLKV

20 + 0.1

 C

250

Pulse width of spikes which must be suppressed by the input

filter

tI2KHKL

050

Capacitance for each I/O pin

—10

—

Input current (0 V

V

IN NVDD)

IIN

—± 5

A4

Note:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. CB = capacitance of one bus line in pF.

3. See the MPC8315E PowerQUICC II Pro Integrated Host Processor Family Reference Manual for information on the digital

filter used.

4. I/O pins obstruct the SDA and SCL lines if NVDD is switched off.

VM = Midpoint Voltage (NVDD/2)

tJTIVKH

tJTIXKH

JTAG

External Clock

Output Data Valid

tJTKLOX

tJTKLOZ

tJTKLOV

Input

Data Valid

Output Data Valid

TDI, TMS

TDO

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