MPC8315CVRADDA datasheet(58/106 Pages) FREESCALE

58 / 106 page

MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

assumes that the LVPECL clock driver’s output impedance is 50

R1 is used to DC-bias the LVPECL

outputs prior to AC-coupling. Its value could be ranged from 140

to 240depending on clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-

 termination

resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8315E SerDes

reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak).

For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock

input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25

Please

consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a

particular clock driver chip.

Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with MPC8315E SerDes reference clock

input’s DC requirement.

Figure 46. Single-Ended Connection (Reference Only)



SD_REF_CLK

Clock Driver

100

differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK

Driver Chip

MPC8315E

10 nF



SD_REF_CLK

100

differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

Single-Ended

CLK Driver Chip

MPC8315E



Total 50

Assume clock driver’s

output impedance is about 16





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