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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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82563EB датащи(PDF) 38 Page - Intel Corporation |
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82563EB датащи(HTML) 38 Page - Intel Corporation |
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38 / 52 page  82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon 32 4.8 Reset and Initial Clock Timing PHY_PWR_GOOD must be low throughout the time that the power supplies are ramping. This guarantees that the 82563EB/82564EB resets cleanly. Figure 10. 82563EB/82564EB Reset Timing Table 32. Specification for External Clock Oscillator Parameter Name Symbol Value Conditions Frequency fo 25.0 [MHz] @25 [°C] Swing Vp-p 3.3 ± 0.3 [V] - Frequency Tolerance ∆f/fo ±30 [ppm] -0 to +70 [°C] Operating Temperature Topr -0 to +70 [°C] - Aging ∆f/fo ±5 ppm per year - DVDD (1.2V) PHY _PWR _GOOD XTAL1 Tppg Txoc PHY _CLK _OUT Oscillator Stable Power Stable Tpco AVDD, AVDDF (1.9V) VDDO, AVDDR (3.3V) |
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