©2012 Silicon Storage Technology, Inc.

DS25024C

10/12

13

8 Mbit 1.8V SPI Serial Flash

SST25WF080

Not Recommended for New Designs

High-Speed-Read (75 MHz)

The High-Speed-Read instruction supporting up to 75 MHz Read is initiated by executing an 8-bit com-

duration of the High-Speed-Read cycle. See Figure 8 for the High-Speed-Read sequence.

Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci-

fied address location. The data output stream is continuous through all addresses until terminated by a

low-to-high transition on CE#. The internal address pointer will automatically increment until the high-

est memory address is reached. Once the highest memory address is reached, the address pointer

will automatically increment to the beginning (wrap-around) of the address space. For example, for 2

Mbit density, once the data from address location 7FFFFH is read, the next output will be from address

location 000000H.

Figure 8: High-Speed-Read Sequence

1203 F07.0

CE#

SO

SI

SCK

ADD.

012 34 5

6 7 8

ADD.

ADD.

0B

HIGH IMPEDANCE

15 16

23 24

31 32

39 40

47 48

55 56

63 64

N+2

N+3

N+4

N

N+1

X

MSB

MODE 0

MODE 3

80

71 72

MSB