©2012 Silicon Storage Technology, Inc.

DS25024C

10/12

7

8 Mbit 1.8V SPI Serial Flash

SST25WF080

Not Recommended for New Designs

Reset/Hold Mode

The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/

HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected

option where an Enable-Hold instruction enables the Hold mode. Once selected as a hold pin

(HOLD#), the RST#/HOLD# pin will be configured as a HOLD# pin, and goes back to RST# pin only

after a power-off and power-on sequence.

Reset

If the RST#/HOLD# pin is used as a reset pin, RST# pin provides a hardware method for resetting the

device. Driving the RST# pin high puts the device in normal operating mode. The RST# pin must be

the device is in reset. A successful reset will reset the status register to its power-up state. See Table 4

for default power-up modes. A device reset during an active Program or Erase operation aborts the

operation and data of the targeted address range may be corrupted or lost due to the aborted erase or

program operation. The device exits AAI Programming Mode in progress and places the SO pin in high

impedance state.

Figure 5: Reset Timing Diagram

Table 2: Reset Timing Parameters

Symbol

Parameter

Min

Max

Units

1. For reset while in a Programming or Erase mode, the reset pulse must be >5µs

Reset Pulse Width

100

ns

Reset to High-Z Output

107

ns

Reset Recovery from Read

100

ns

Reset Recovery from Program

10

µs

Reset Recovery from Erase

1

ms

T2.25024

1203 F04.0

CE#

SO

SI

SCK

RST#