©2012 Silicon Storage Technology, Inc.

DS25024C

10/12

11

8 Mbit 1.8V SPI Serial Flash

SST25WF080

Not Recommended for New Designs

Instructions

Instructions are used to read, write (Erase and Program), and configure the SST25WF080. The

instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-

Enable (WREN) instruction must be executed prior to Byte-Program, Auto Address Increment (AAI)

programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The com-

plete instructions are provided in Table 6. All instructions are synchronized off a high-to-low transition

of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE#

must be driven low before an instruction is entered and must be driven high after the last bit of the

instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any

low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the

instruction in progress and return the device to standby mode. Instruction commands (Op Code),

addresses, and data are all input from the most significant bit (MSB) first.

Table 6: Device Operation Instructions for SST25WF080

Instruction

Description

1. One bus cycle is eight clock periods.

Address

Dummy

Cycle(s)

Data

Cycle(s)

Maximum

Frequency

Read

Read Memory

0000 0011b (03H)

3

0

1 to

∞

33 MHz

High-Speed

Read

Read Memory at Higher Speed

0000 1011b (0BH)

3

1

1 to

∞

75 MHz

4 KByte Sec-

Erase 4 KByte of memory array

0010 0000b (20H)

3

0

0

32 KByte

Erase 32 KByte block

of memory array

0101 0010b (52H)

3

0

0

64 KByte

Erase 64 KByte block

of memory array

1101 1000b (D8H)

3

0

0

Chip-Erase

Erase Full Memory Array

0110 0000b (60H) or

1100 0111b (C7H)

00

0

Byte-Program To Program One Data Byte

0000 0010b (02H)

3

0

1

AAI-Word-

Auto Address Increment

Programming

1010 1101b (ADH)

3

0

2 to

∞

Read-Status-Register

0000 0101b (05H)

0

0

1 to

∞

Enable-Write-Status-Register

0110 0000b (50H)

0

0

0

WRSR

Write-Status-Register

0000 0001b (01H)

0

0

1

Write-Enable

0000 0110b (06H)

0

0

0

WRDI

Write-Disable

0000 0100b (04H)

0

0

0

Read-ID

1001 0000b (90H) or

1010 1011b (ABH)

30

1 to

∞

EBSY

Enable SO to output RY/BY#

status during AAI programming

0111 0000b (70H)

0

0

0

DBSY

Disable SO to output RY/BY#

status during AAI programming

1000 0000b (80H)

0

0

0

JEDEC-ID

JEDEC ID read

1001 1111b (9FH)

0

0

3 to

∞

EHLD

Enable HOLD# pin functionality

of the RST#/HOLD# pin

1010 1010b (AAH)

0

0

0

T6.0 25024