©2012 Silicon Storage Technology, Inc.

DS25024C

10/12

12

8 Mbit 1.8V SPI Serial Flash

SST25WF080

Not Recommended for New Designs

Read (33 MHz)

The Read instruction, 03H, supports up to 33 MHz Read. The device outputs a data stream starting

from the specified address location. The data stream is continuous through all addresses until termi-

nated by a low-to-high transition on CE#. The internal address pointer automatically increments until

the highest memory address is reached. Once the highest memory address is reached, the address

pointer automatically increments to the beginning (wrap-around) of the address space. For example,

for 8 Mbit density, once the data from the address location FFFFFH is read, the next output is from

address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, fol-

ure 7 for the Read sequence.

Figure 7: Read Sequence

6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of

programmed into the

7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

8. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides back-

ward compatibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs.

turer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.

1203 F06.0

CE#

SO

SI

SCK

ADD.

0 1 234 5 6 78

ADD.

ADD.

03

HIGH IMPEDANCE

15 16

23 24

31 32

39 40

70

47

48

55 56

63 64

N+2

N+3

N+4

N

N+1

MSB

MSB

MSB

MODE 0

MODE 3

DOUT