DAC8420

REV. 0

–15–

DAC8420 to M68HC11 Interface Assembly Program

PORTC EQU $1003 Port C control register

*

“0,0,0,0;0,CLSEL,CLR,CS”

DDRC EQU $1007 Port C data direction

PORTD EQU $1008 Port D data register

*

“0,0,LD,SCLK;SDI,0,0,0”

DDRD EQU $1009 Port D data direction

SPCR EQU $1028 SPI control register

*

“SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0”

SPSR EQU $1029 SPI status register

*

“SPIF,WCOL,0,MODF;0,0,0,0”

SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter

*

* SDI RAM variables: SDI1 is encoded from 0 (Hex) to CF (Hex)

* To select: DAC A – Set SDI1 to $0X

DAC B – Set SDI1 to $4X

DAC C – Set SDI1 to $8X

DAC D – Set SDI1 to $CX

SDI2 is encoded from 00 (Hex) to FF (Hex)

*

DAC requires two 8-bit loads – Address + 12 bits

SDI1 EQU $00 SDI packed byte 1 “A1,A0,0,0;MSB,DB10,DB9,DB8”

SDI2 EQU $01 SDI packed byte 2

“DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0”

* Main Program

ORG $C000 Start of user’s RAM in EVB

INIT LDS #$CFFF Top of C page RAM

* Initialize Port C Outputs

LDAA #$07 0,0,0,0;0,1,1,1

*

CLSEL-Hi, CLR-Hi, CS-Hi

*

To reset DAC to ZERO-SCALE, set CLSEL-Lo ($03)

*

To reset DAC to MID-SCALE, set CLSEL-Hi ($07)

STAA PORTC Initialize Port C Outputs

LDAA #$07 0,0,0,0;0,1,1,1

STAA DDRC CLSEL, CLR, and CS are now enabled as outputs

* Initialize Port D Outputs

LDAA #$30 0,0,1,1;0,0,0,0

*

LD

-Hi,SCLK-Hi,SDI-Lo

STAA PORTD Initialize Port D Outputs

LDAA #$38 0,0,1,1;1,0,0,0

STAA DDRD LD,SCLK, and SDI are now enabled as outputs

* Initialize SPI Interface

LDAA #$5F

STAA SPCR SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32

* Call update subroutine

BSR UPDATE Xfer 2 8-bit words to DAC-8420

JMP $E000 Restart BUFFALO

* Subroutine UPDATE

UPDATE PSHX

Save registers X, Y, and A

PSHY

PSHA

* Enter Contents of SDI1 Data Register (DAC# and 4 MSBs)

LDAA #$80 1,0,0,0;0,0,0,0

STAA SDI1 SDI1 is set to 80 (Hex)

* Enter Contents of SDI2 Data Register

LDAA #$00 0,0,0,0;0,0,0,0

STAA SDI2 SDI2 is set to 00 (Hex)

LDX #SDI1 Stack pointer at 1st byte to send via SDI

LDY #$1000 Stack pointer at on-chip registers

* Clear DAC output to zero

BCLR PORTC,Y $02 Assert CLR

BSET PORTC,Y $02 Deassert CLR

* Get DAC ready for data input

BCLR PORTC,Y $01 Assert CS

TFRLP LDAA 0,X Get a byte to transfer via SPI

STAA SPDR Write SDI data reg to start xfer

WAIT LDAA SPSR Loop to wait for SPIF

BPL WAIT SPIF is the MSB of SPSR

*

(when SPIF is set, SPSR is negated)

INX

Increment counter to next byte for xfer

CPX #SDI2+ 1 Are we done yet ?

BNE TFRLP If not, xfer the second byte

* Update DAC output with contents of DAC register

BCLR PORTD,Y 520 Assert LD

BSET PORTD,Y $20 Latch DAC register

BSET PORTC,Y $01 De-assert CS

PULA When done, restore registers X, Y & A

PULY

PULX

RTS

** Return to Main Program **