DAC8420

REV. 0

–14–

DAC-8420

DIGITAL

CONTROL

4

9

15

16

14

12

11

10

8

2

3

6

7

1

5

DAC A

DAC B

DAC C

DAC D

VOUTA

VOUTB

VOUTC

VOUTD

DIGITAL INPUTS

GND

VREFLO

0.1µF

+5V SUPPLY

VREFHI

VSS

5

4

6

9

8

11

10

2

1

14

3

12

CMP-04

13

0.1µF

+5V

+5V

604

Ω

+5V

RED LED

604

Ω

OUT A

OUT B

VINA

VINB

RED LED

REF-43

GND

VIN

+5V SUPPLY

2.5V

0.1µF

6

2

4

7

C1

C2

C3

C4

Figure 31. Dual Programmable Window Comparator

MC68HC11 Microcontroller Interfacing

Figure 32 shows a serial interface between the DAC8420 and

the MC68HC11 8-bit microcontroller. The SCK output of the

68HC11 drives the CLK input of the DAC, and the MOSI port

outputs the serial data to load into the SDI input of the DAC.

The port lines PD5, PC0, PC1, and PC2 provide the controls to

the DAC as shown.

PC2

PC1

PC0

(PD5) SS

SCK

MOSI

MC68HC11*

CLSEL

CLR

CS

LD

CLK

SDI

DAC-8420*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 32. MC68HC11 Microcontroller Interface

For correct operation, the 68HC11 should be configured such

that its CPOL bit and CPHA bit are both set to 1. In this con-

figuration, serial data on MOSI of the 68HC11 is valid on the

rising edge of the clock, which is the required timing for the

DAC8420 Data is transmitted in 8-bit bytes (MSB first), with

only eight rising clock edges occurring in the transmit cycle. To

load data to the DAC8420’s input register, PC0 is taken low

and held low during the entire loading cycle. The first 8 bits are

shifted in address first, immediately followed by another 8 bits

in the second least-significant byte to load the complete 16-bit

word. At the end of the second byte load, PC0 is then taken

high. To prevent an additional advancing of the internal shift

register, SCK must already be asserted before PC0 is taken

high. To transfer the contents of the input shift register to the

DAC register, PD5 is then taken low, asserting the LD input of

the DAC and completing the loading process. PD5 should re-

turn high before the next load cycle begins. The DAC8420’s

CLR

input, controlled by the output PC1, provides an asyn-

chronous clear function.